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The GT Readout Platform aims to provide a readout for use with new pixel detectors developed at SLAC (≥ 2023), which use high-speed (> 1 Gbit/s) gigabit transceivers for their data output. See for example the SparkPix-IO prototype. It consists of three main parts (shown in the block diagram below):
The sections below describe the platform in more detail. Use the table of contents below to quickly find a specific section you might be looking for or use one of the useful resources on the right for quick access. |
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Table of Contents maxLevel 2 exclude \b(?:Table of contents|Useful resources|Pages under this one)\b|\*
Children Display |
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Requirement | ePixUHR | SparkPix-S | SparkPix-ED |
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Frame rate | 100 kfps | 1 Mfps | 1 Mfps |
Power supplies | 2.5 V Analog | 2.5 V Analog | 1.3 V (AS/DS/IO) |
Power for each supply | ePixUHR - 35 kHz | SparkPix-S: supply/ground and power consumption | t.b.d. |
Number of GT IOs per ASIC | 8 (outputs) | 8 (outputs) 1 clock in | t.b.d |
Expected I/O speed | 5.25 Gbit/s | 5.25 Gbit/s | 10 Gbit/s |
Total data bandwidth | 42 Gbit/s | 42 Gbit/s | 80 Gbit/s |
There are three targeted cameras for this project:
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2x2 ePix/SparkPix | 1M ePix | 2M SparkPix S | |||
Parameter (estimated) | Small Camera | Small Camera | Super tile | Super tile | Quad Camera |
Pixels | 129,024 px | 516,096 px | 967,680 | 1,161,216 px | 2,064,384 px |
Rate | 35 kHz / 100 kHz | 1 MHz | 35 kHz / 100 kHz | 35 kHz / 100 kHz | 1 MHz |
Focal Plane Area | 4 cm x 4 cm | 4 cm x 4 cm | 12 cm x 10 cm | 12 cm x 12 cm | 8 cm x 8 cm |
Front side footprint (window) | 5 cm x 5 cm | 5 cm x 5 cm | 14 cm x 1 2cm | 14 cm x 14 cm | 10 cm x 10 cm |
Power (only ASIC) | 0.016 kW/??? | 0.021 kW | 0.130 kW/??? | 0.144 kW/??? | 0.084 kW |
Weight | 1.5 kg | 1.5 kg | 9 kg | 10 kg | 6 kg |
Data volume | 56 Gbit/s/ 160 Gbit/s | 160 Gbit/s | 420 Gbit/s / 1190 Gbit/s | 504 Gbit/s / 1440 Gbit/s | 640 Gbit/s |
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From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbit/s @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbit/s From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbit/s / 40 Gbit/s @140k - 4 ASIC (35kHz/100kHz): 56 Gbit/s / 160 Gbit/s @1M - 30 ASIC (35kHz/100kHz): 420 Gbit/s / 1.19 Tbit/s @1.1M - 36 ASIC (35kHz/100kHz): 504 Gbit/s / 1.44 Tbit/s @4M - 144 ASIC (35kHz/100kHz): 2 Tbit/s/ 5.76 Tbit/s @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbit/s / 23 Tbit/s |
ASIC Power Requirement | Analog Section | Digital Section | I/O Section | 0.6V Sink | Analog TPS | |||||
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ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | |
Voltage | 1.3 V | 1.3 V | 1.3 V | 1.3 V | 1.3 V | 1.3 V | N/A | 0.6 V | 2.5 V | 2.5 V |
Required current | 10A (= 2.5 A * 4 ASIC) | 13.4 A (= 3.35 A * 4 ASIC) | 1.872 A (= 0.468 A * 4 ASIC) | 2.0 A (= 0.5 A * 4 ASIC) TBD | 1.6 A (= 0.4 * 4 ASIC) [1RX, 8TX, 8serializer and 2cm clkspine : ~ 317mA] | N/A | -8 A | 0.4 A (=0.1 * 4 ASIC) | ||
System Requirement | +1.3 V @ +17.5 A (Adding +30% current for PVT variation) | +1.3 V @ +3 A (Adding +30% current for PVT variation) [waiting for the new digital design] | +1.3 V @ +2.5 A (Adding +30% current for PVT variation) | +0.6 V @ -11 A This current is not provided by the LDO. But it passes through it. (Adding +30% current for PVT variation) | +2.5 V @ +0.5 A (Adding +30% current for PVT variation) |
ePixUHR 140k 2x2 Detector Specs | ePixUHR 1.1M 6x6 Detector Specs | ePixUHR 1M 6x5 Detector Specs | SparkPix-S 500k 2x2 Detector Specs | SparkPix-S 2M 4x4 Detector Specs | KU15P (-A1760) Kintex Ultrascale+ | KU15P (-A1156) Kintex Ultrascale+ FPGA USED IN ePixHR250M | KU15P (-E1517) Kintex Ultrascale+ | XCVU160 (-C2104) Virtex Ultrascale | XCVU190 (- A2577 ) Virtex Ultrascale | VU13P (-A2577) Virtex Ultrascale+ | |
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General IO (HD, HP) | 96 HD, 416 HP | 48 HD, 486 HP | 96 HD, 416 HP | 52 HD, 364 HP | 0 HD, 448 HP | 0 HD, 448 HP | |||||
High Speed GTs (GTH/GTY) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbit/s / 275Gbit/s (1 Amphenol Transceiver) Total: 48 High Speed GTs | - ASIC data: 288 = 8 lanes * 36 ASIC - Spare outputs : 0 - PGP communication: 72 = 12* 1.44 Tbit/s / 275Gbit/s (6 Amphenol Transceivers) Total: 360 High Speed GTs | - ASIC data: 240 = 8 lanes * 30 ASIC - Spare outputs : 0 - PGP communication: 72 = 12 lanes * 1.19 Tbit/s / 275Gbit/s (6 Amphenol Transceivers) Suggested 3 transceivers 1.4x compression in the detector Total: 312 High Speed GTs (If considering 5x2 Modules, 104 GTs each) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbit/s / 275Gbit/s (1 Amphenol Transceivers) Total: 48 High Speed GTs | - ASIC data: 128 = 8 lanes * 16 ASIC - Spare outputs : 0 - PGP communication: 24* = 12* 495 Gbit/s / 275Gbit/s (2 Amphenol Transceivers) Total: 152 High Speed GTs | 76 (44 GTH/32 GTY) | 28 | 56 (32 GTH/24 GTY) | 104 (52 GTH/52 GTY) | 120 (60 GTH/60 GTY) | 128 (0 GTH/128 GTY) |
Total Block RAM | 34.6 Mb | 34.6 Mb | 34.6 Mb | 115.2 Mb | 132.9 Mb | 94.5 Mb | |||||
UltraRam, HBM | 36 Mb, None | 36 Mb, None | 36 Mb, None | None, None | None, None | 360 Mb, None | |||||
Transceiver Speed (GTH, GTY) | > 10 Gbit/s | > 10 Gbit/s | > 10 Gbit/s | > 10 Gbit/s | > 10 Gbit/s | GTH 16.3 Gbit/s GTY 32.75 Gbit/s Transceivers | GTH 16.3 Gbit/s GTY 16.3 Gbit/s Transceivers | GTH 16.3 Gbit/s GTY 32.75 Gbit/s Transceivers | GTH 16.3 Gbit/s GTY 30.5 Gbit/s Transceivers | GTH 16.3 Gbit/s GTY 30.5 Gbit/s Transceivers | GTY 32.75 Gbit/s Transceivers |
Size | The PCB width is (preferably) 65 mm (2.56’’) | 42.5 x 42.5 mm | 35 x 35 mm | 40 x 40 mm | 47.5x47.5 mm | 52.5 x 52.5 mm | 52.5 x 52.5 mm | ||||
Cost | 6-10 k$ | 5-9 k$ | 6-10k$ | 40 k$ | 50-70 k$ | 60-110 k$ | |||||
Comments | This is fine for the 2x2 Systems. This is fine for the SparkPix-S 4x4 | The number of GTs in this FPGA does not fit any of the cameras we are targetting | This is fine for the 2x2 Systems. For the larger systems we need more than 3 FPGAs | This is fine for the 2x2 Systems. | This is fine for the 2x2 Systems (assuming we can fit the real estate). | This is fine for the 2x2 Systems.(assuming we can fit the real estate) |
*Done considering 1% Occupancy instead of maxing out the transceivers
UHR 2x2 | SparkPix S 2x2 | SparkPix S 4x4 | UHR 5x6 | UHR 6x6 | ||
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Requirements Characteristics | 48 GTs | 48 GTs | 152 GTs | 312 GTs | 360 GTs | |
KU15P (-A1156) Kintex U+ | 28 GTs / 352 mm2 / 10k$ | ❌ | ❌ | ❌ | ❌ | ❌ |
KU15P (-E1517) Kintex U+ | 56 GTs / 402 mm2 / 10k$ | ✅ | ✅ | ❌ | ❌ | ❌ |
KU15P (-A1760) Kintex U+ | 76 GTs / 42.52 mm2 / 10k$ | ✅ | ✅ | ✅ (2 FPGA) | ❌ | ❌ |
XCVU160 (-C2104) Virtex U | 104 GTs / 47.52 mm2 / 40k$ | ✅ | ✅ | ✅ (2 FPGA) | ✅ (1 FPGA/module) | ❌ |
XCVU190 (- A2577 ) Virtex U | 120 GTs / 47.52 mm2 / 70k$ | ✅ | ✅ | ✅(2 FPGA) | ✅ (1 FPGA/module) | ✅ (1 FPGA/module) |
VU13P (-A2577) Virtex U+ | 128 GTs / 52.52 mm2 / 110k$ | ✅ | ✅ | ✅(2 FPGA) | ✅ (1 FPGA/module) | ✅ (1 FPGA/module) |
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ePixUHR 140k 2x2 Detector SystemSparkPix S – 500k 2 x 2 ASIC Detector System |
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From Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
Name | Voltage |
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VCCINT | 0.85 V |
VCCINT_IO | 0.85 V |
VCCBRAM | 0.85 V |
VCCAUX | 1.8 V |
VCCAUX_IO | 1.8 V |
MGTVCCAUX_LN/LS/RN/RS | 1.8 V |
VCCADC | 1.8 V |
MGTAVCC_LN/LS/RN/RS | 0.9 V |
MGTAVTT_LN/LS/RN/RS | 1.2 V |
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Power calculation SpreadSheet: UltraScalePlus_XPE_2023_140kpx.xlsm |
A GUI from Linear Technologies (now Analog Devices) called LTPowerPlanner has been used to calculate all the required currents and voltages in the system. It also calculates the estimated losses and efficiency of the system.
Power block diagram | LTPowerPlanner | ||||||||||
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Table of Contents
Useful resources
Jira issues in progress
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The tasks and questions below should be looked at as soon as possible since they might be blocking |
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title | Archived questions |
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Precision Current Sources and Sinks Using Voltage References
2.5V Analog
1.3V (AS/DS/IO)
2.5V Analog
1.3V (AS/DS/IO)
0.6V (Current sink!)
8 (outputs)
1 clock in
t.b.d
(The current agreement is to have 8 outputs)
Total data bandwidth
There are three targeted cameras for this project:
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2x2 ePix/SparkPix
1M ePix
2M SparkPix S
Parameter (estimated)
Small Camera
ePixHR/UHR – 140k
2x2 ASIC
Small Camera
SparkPix S – 500k
2x2 ASIC
Super tile
ePixHR/UHR – 1M
6x5 ASIC
Super tile
ePixHR/UHR – 1.1M
6x6 ASIC
Quad Camera
SparkPix S – 2M
4x4 ASIC
Pixels
129,024 px
(168 *192*4)
540,672 px
(352*384*4)
967,680
(168 *192*30)
1,161,216 px
(168 *192*36)
2,162,688 px
(352*384*16)
Rate
35kHz / 100kHz
1MHz
35kHz / 100kHz
35kHz / 100kHz
1MHz
Focal Plane Area
4cm x 4cm
4cm x 4cm
12cm x 10cm
12cm x 12cm
8cm x 8cm
Front side footprint (window)
5cm x 5cm
5cm x 5cm
14cm x 12cm
14cm x 14cm
10cm x 10cm
Power (only ASIC)
0.016 kW/???
Weight
1.5kg
1.5kg
9Kg
10kg
6kg
Data volume
56 Gbps/ 160 Gbps
160 Gbps
420 Gbps/ 1190 Gbps
504 Gbps/ 1440 Gbps
640 Gbps
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From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps @140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps @1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps @1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps @4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps |
ASIC Power Requirement
Analog Section
Digital Section
I/O Section
0.6V Sink
Analog TPS
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
ePixUHR 140k 2x2 Detector
SparkPix-S 500k 2x2 Detector
Voltage
1.3 V
1.3V
1.3V
1.3V
1.3V
1.3V
??? Maybe
0.6 V
2.5 V
2.5V
Required current
10A
(= 2.5 A* 4 ASIC)
13.4 A
(= 3.35A * 4 ASIC)
- Old digital design:
1.2 A (= 0.3 A * 4 ASIC)
-New digital design
????
- Old digital design
2.0 A (= 0.5 A * 4 ASIC)
-New digital design
????
1.6 A
(= 0.4 * 4 ASIC)
[1RX, 8TX, 8serializer and 2cm clkspine : ~ 317mA]
??? (If existing lower or equal than SparkPixS)
-8 A
(= -2A * 4 ASIC)
0.4 A
(=0.1 * 4 ASIC)
System Requirement
+1.3 V @ +17.5 A
(Adding +30% current for PVT variation)
+1.3 V @ +3 A
(Adding +30% current for PVT variation)
[waiting for the new digital design]
+1.3 V @ +2.5 A
(Adding +30% current for PVT variation)
+0.6 V @ -11 A
!this current is not provided by the LDO. But it passes through it.
(Adding +30% current for PVT variation)
+2.5 V @ +0.5 A
(Adding +30% current for PVT variation)
ePixUHR 140k
2x2 Detector
Specs
ePixUHR 1.1M
6x6 Detector
Specs
ePixUHR 1M
6x5 Detector
Specs
SparkPix-S 500k
2x2 Detector
Specs
SparkPix-S 2M
4x4 Detector
Specs
KU15P (-A1760)
Kintex Ultrascale+
KU15P (-A1156)
Kintex Ultrascale+
FPGA USED IN ePixHR250M
KU15P (-E1517)
Kintex Ultrascale+
XCVU160 (-C2104)
Virtex Ultrascale
XCVU190 (-A2577)
Virtex Ultrascale
VU13P (-A2577)
Virtex Ultrascale+
General IO (HD, HP)
96 HD, 416 HP
48 HD, 486 HP
96 HD, 416 HP
52 HD, 364 HP
0 HD, 448 HP
0 HD, 448 HP
High Speed GTs (GTH/GTY)
- ASIC data:
32 = 8 lanes * 4 ASIC
- Spare outputs :
4
- PGP communication:
12 = 12* 160 Gbps/ 275Gbps
(1 Amphenol Transceiver)
Total:
48 High Speed GTs
- ASIC data:
288 = 8 lanes * 36 ASIC
- Spare outputs :
0
- PGP communication:
72 = 12* 1.44 Tbps/ 275Gbps
(6 Amphenol Transceivers)
Total:
360 High Speed GTs
- ASIC data:
240 = 8 lanes * 30 ASIC
- Spare outputs :
0
- PGP communication:
72 = 12 lanes * 1.19 Tbps/ 275Gbps
(6 Amphenol Transceivers)
Suggested 3 transceivers 1.4x compression in the detector
Total:
312 High Speed GTs
(If considering 5x2 Modules, 104 GTs each)
- ASIC data:
32 = 8 lanes * 4 ASIC
- Spare outputs :
4
- PGP communication:
12 = 12* 160 Gbps/ 275Gbps
(1 Amphenol Transceivers)
Total:
48 High Speed GTs
- ASIC data:
128 = 8 lanes * 16 ASIC
- Spare outputs :
0
- PGP communication:
24* = 12* 495 Gbps/ 275Gbps
(2 Amphenol Transceivers)
Total:
152 High Speed GTs
76
(44 GTH/32 GTY)
28
(20 GTH/8 GTY)
56
(32 GTH/24 GTY)
104
(52 GTH/52 GTY)
120
(60 GTH/60 GTY)
128
(0 GTH/128 GTY)
Total Block RAM
34.6 Mb
34.6 Mb
34.6 Mb
115.2 Mb
132.9 Mb
94.5 Mb
UltraRam, HBM
36 Mb, None
36 Mb, None
36 Mb, None
None, None
None, None
360 Mb, None
Transceiver Speed
(GTH, GTY)
> 10 Gbps
> 10 Gbps
> 10 Gbps
> 10 Gbps
> 10 Gbps
GTH 16.3 Gb/s
GTY 32.75 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 16.3 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 32.75 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 30.5 Gb/s
Transceivers
GTH 16.3 Gb/s
GTY 30.5 Gb/s
Transceivers
GTY 32.75 Gb/s
Transceivers
Size
The PCB width is (preferably) 65 mm (2.56’’)
42.5 x 42.5 mm
35 x 35 mm
40 x 40 mm
47.5x47.5 mm
52.5 x 52.5 mm
52.5 x 52.5 mm
Cost
6-10 k$
5-9 k$
6-10k$
40 k$
50-70 k$
60-110 k$
Comments
This is fine for the 2x2 Systems.
This is fine for the SparkPix-S 4x4
The number of GTs in this FPGA does not fit any of the cameras we are targetting
This is fine for the 2x2 Systems.
For the larger systems we need more than 3 FPGAs
This is fine for the 2x2 Systems.
This is fine for the 2x2 Systems (assuming we can fit the real estate).
This is fine for the 2x2 Systems.(assuming we can fit the real estate)
*Done considering 1% Occupancy instead of maxing out the transceivers
Requirements
Characteristics
KU15P (-A1156) Kintex U+
title | FPGA Size Comparison |
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title | Proposed System solutions |
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From Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
title | KU15P power estimation |
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Power calculation SpreadSheet: UltraScalePlus_XPE_2023_140kpx.xlsm
We would like to match the ePixHRM board dimensions to reuse cooling
Side entrance detector
2.56x1.95"
Board
Domain
Portion
Final Voltages
LDOs
DC/DC
DC/DC
Analog
Analog
ASIC
G_AS_0
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
LT8648S x2
42V, 15A Synchronous Step-Down Silent Switcher 2
Max Current = 15*2 = 30A
(Around 93% efficiency for 24 to 6V at max load)
← +24 V
The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS.
The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W.
If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W.
The power drawn by the rest of analog voltages should be less than 2W.
So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W.
Considering the efficiency curves of the DC/DC converters:
34/85%/93% =
43W Total Analog Power
G_AS_1
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
G_AS_2
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
G_AS_3
1.3V @4.4A
← +1.3V
LT1764 x2 (LDO)
Max 6A (= 3A x2)
← +1.8V (TBD)
G_VG_0
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
← +2.5V
LT3086 (LDO)
Max 2.1A
← +3V
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(>90% efficiency for this loads)
← +6 V
G_VG_1
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
G_VG_2
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
← +6 V
G_VG_3
0.6V @ -2.75A
← +0.6V
LT3091 x2 (LDO)
Max 3.0A (= 1.5A x2)
G_AS_2V5
2.5V @ <0.5 A
← +2.5V
DAC/ADC/Misc.
VDD_5V
+5V @ <1A?
5 W
← 5V?
LT3086 (LDO)
Max 2.1A
VDD_3V3
+3.3V @ <1A?
3.3 W
← +3.3V?
LT3086 (LDO)
Max 2.1A
VDD_1V8
+1.8V @ <1A?
1.8 W
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G_DS_0
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← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
LT8648S x2
42V, 15A Synchronous Step-Down Silent Switcher 2
Max Current = 15*2 = 30A
(Around 93% efficiency for 24 to 6V at max load)
← +24 V
For the digital consumption of the ASIC we do not have precise numbers regarding the new CML logic.
Let's assume a double consumption w.r.t the LVDS design.
1.3V*6A = 8W
LDO losses = 0.5*6A = 3W
11W / 85% / 93% = 14W(ASIC Digital)
Worst case scenario, the remaining electronics will draw 1A, multiplied by 5.5V = 5.5W, which before the DCDC will become 5.5W /85 = 7W
42.5W Total Digital Power
G_DS_X
1.3V @???A (CML simulations?)
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
G_IO_0
1.3V @???A(CML simulations?)
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
TPSM5D1806 (DC/DC)
PMIC
4.5-V to 15-V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
← +6 V
G_IO_X
1.3V @???A(CML simulations?)
← +1.3V
LT3086 x2 (LDO)
Max 4.2A (= 2.1A x2)
← +1.8V (TBD)
Digital
FPGA
VCCINT
0.85V @7.05 A
6 W
← +0.85V
LMZ31520 DC/DC Buck converter
3V to 14.5V input
20A
(Around 90% efficiency)
Max 17 W_out, 19 W_in
← +5 V
Max ~60 W
LT8638S x2
42V, 10A Synchronous Step-Down Silent Switcher 2
Max Current = 10*2 = 20A
(Around 93% efficiency for 24 to 5V at max load)
Max 100 W_out, 110 W_in
← +24 V
Regarding the FPGA considering a worst case efficiency of the DC/DC:
17.1W /85%/93% = 21.5W (FPGA)
VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX
1.8V @0.7A
1.3 W
← +1.8V
TPSM5D1806 (DC/DC)
PMIC
4.5V to 15V input
Dual 6A output
(85% efficiency for max load at Vout = 1.8V)
Max 16 W_out, 19 W_in
MGTAVCC +MGTYAVCC
0.9V @3.7A
3.3 W
← +0.9V
VCC_1.2V + MGTAVTT + MGTYAVTT
1.2V @5.5A
6.6 W
← +1.2V
TPSM5D1806 (DC/DC)
PMIC
4.5V to 15V input
Parallel 12A output
(Between 80% and 90% efficiency)
Max 15 W_out, 19 W_in
DAC/ADC/Misc.
VDD_5V
+5V @ <1A
5 W
← 5V?
LT3086 (LDO)
Max 2.1A
← +5V
VDD_3V3
+3.3V @ <1A
3.3 W
← +3.3V?
LT3086 (LDO)
Max 2.1A
VDD_1V8
+1.8V @ <1A
1.8 W
← +1.8V?
LT3086 (LDO)
Max 2.1A
Component
Product number
Quantity
Input Voltage
Output Voltage
Max Current
Comment
Product number | Type | Input Voltage | Output Voltage | Max Current | Comment |
LT8638S | Buck | 2.8V to 42V | 0.6V to 42V | 10A | DC/DC Step Down converter. Parallel operation possible. (same as used in Power & communication board (PC_261_101_26_C00) |
TPSM5D1806 | Buck | 4.5V to 15V | 0.5V to 5.5V | Dual 6A / Single 12A | DC/DC PMIC |
LMZ31520 | Buck | 3V to 14.5V | 0.6V to 3.6V | 20A | DC/DC Buck converter. 30A version LMZ31530. |
LT3086 | LDO | 1.4V to 40V | 0.4V to 32V | 2.1A | Low Output Noise: 40µVRMS (10Hz to 100kHz). Parallel operation possible. |
LT3091 | LDO | –1.5V to –36V | 0V to –32V | -1.5A | Negative Linear Regulator. Low Output Noise: 18µVRMS (10Hz to 100kHz). Parallel operation possible. |
https://webench.ti.com/power-designer/switching-regulator
There are optional bypass jumpers on the analog board, as shown in the diagram above, for providing power to the ASIC directly from the LT8638S switching regulators. This will bypass the LDOs and can be used to test the performance of the ASIC when it's powered from a "dirtier" power source.
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Make sure to adjust the output voltage of the switching regulators from 1.8 V to 1.3 V before powering up with an ASIC as the 1.8 V can cause permanent damage! The LDOs that are bypassed should also be removed from the board. |
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Requirement | Parameters | Notes |
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Power supply | 24 V consistent with the HR detector | |
Mechanical size | We would like to match the ePixHRM board dimensions to reuse cooling Side entrance detector
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Digital board | 2.56 x 5.265" | |
Power and communication | 2.56 x 5.240" | |
Carrier | 2.56 x 1.95" |
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TOTAL = 13 * 4( n.Asics ) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP |
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For single ended → check the electrical specification |
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Functionality | Observations | link |
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Carrier to analog board |
| https://docs.google.com/spreadsheets/d/1b_nFUIKPOlVZJwAgv-RxHJQhuoHP3wuV?rtpof=true&usp=drive_fs |
Analog to digital board |
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External power supply |
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Optical transceiver |
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See
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Current cooling block | Updated cooling block |
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The photo below shows the current cooling block designs (straight and angled), which is for a 30x6 SEAM/SEAF connector between analog and digital board. | The screenshot below shows that a 40x8 SEAM/SEAF connector can fit by extending the cutout in the cooling block without interfering with the pipe. Orange lines are the outline of the cooling block and the pipes in it. The new connector is 10*1.27 = 12.7 mm longer. |
Team center DSG-000074563* DSG-000074553 |
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There are four main clock sources:
The SI53340 clock buffer only buffers the input clock source into four output clocks with low amount of jitter added. The SI5345B is a jitter attenuator and an "any-frequency" multiplier where one input is selected that is fed to a PLL which then feeds multipliers for the individual outputs. Each output can therefore be programmed to different frequencies, which are synchronous with the selected input clock.
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The gigabit transceivers (GTs) in the ASIC require a high-frequency clock (2-3 GHz) with low jitter. There is no PLL inside the ASIC so it has to be provided from an external source (see SparkPix-IOs: fast I/Os prototype (~5 Gb/s) on TSMC 130nm). The proposed architecture will use the GTH transceiver outputs of the Kintex UltraScale+ to generate a "clock" from a static "101010..." bit pattern.
Gliffy Diagram | ||||||
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There are high-speed signals in both directions between the ASICs and the FPGA:
These could either be DC-coupled or AC-coupled, which means that a series capacitor in the order of ~100nF is placed in series with the signal somewhere along the path. It is also called DC-blocking capacitors as described by Dr. Howard Johnson in an article on his website. The question is, where to place the capacitors? Close to the transmitter, in the middle, close to the receiver or somewhere else? In Johnson's article he argues that the main effect of these capacitors will be an impedance mismatch because the package of the capacitor will be bigger than the trace itself and we end up with an impedance that is less than the nominal impedance Z0 of the transmission line. This will result in negative reflections. He then argues that the effect of such a reflection has to be considered in relationship to the symbol baud interval and if it's much less than 1/2 of the baud interval it will have a minimal effect. We are working with up to 6 Gbit/s which gives a baud interval of 167ps. With a propagation delay of around 150 ps/inch (source) it means that to have minimal impact it has to be much less than 1/4 inch (~6 mm), somewhere in the order 1/20 of an inch (~1.2 mm) which is not practical on a PCB with IC packages, passives and routing.
For these high-speed cases it is therefore not the distance of the capacitor from the transmitter that matters, but instead the layout and routing of the traces around the capacitor.The goal is instead to minimize the effect of the capacitor on the impedance of the trace. One example Johnson gives is to reduce the parasitic capacitance underneath the body of the capacitor with a keep-out region in the reference plane underneath. A similar concept is shown in a layout design guide (local pdf copy, see page 30) for an Intel Stratix 10 device.
If we look at the LEAP transceiver that we are using in this project we can see that it has the AC-coupling capacitors on both RX and TX inside the package itself. This probably ensures that the effect of the capacitors is reduced as much as possible and they might use very small package sizes.
In our case it's probably a question of physical constraints that define where we can place the capacitors. For all four ASICs we would need 4*8*2+4*2=72 capacitors for data and clocks. Placing these on the carrier board might be tricky. Having them on the analog board would be a tight fit due to all the power supplies it has. That leaves the digital board which should hopefully have enough space to make a "clean" implementation of these capacitors.
The ASIC timing (SRO, R0, ACQ and INJ) and control (GR_N, SACI_SEL[3..0], SACI_CLK, SACI_CMD and SACI_RSP) are 1.3 V CMOS signals in the ASIC that has be be interfaced with the FPGA banks. In previous systems (e.g. ePixHR10k 2M digital board (TXI)) these were 2.5 V CMOS and were driven directly from HD banks in the Kintex UltraScale+ (except for SACI_SEL and SACI_RSP that were driven via MAX3002 from 1.8 V HP banks).
In short, there are two types of voltage level translators: auto-sensing bidirectional ones with transmission gates that will pull up or down when a rising or falling edge are detected; directional ones which has input receivers in one voltage domain and output drivers in the other voltage domain. The auto-sensing ones seem to lack information about the timing characteristics in the datasheet which is probably because it depends on how it is used and the device that is driving the pins of the translator. The directional ones are probably a better fit for this application where we know the direction and want as high drive strength as possible to propagate from the digital board all the way to the ASIC on the carrier board.
FPGA HD banks | FPGA HP banks | MAX3002 | MAX3378E | TI AXC series | TI TXU series | TI TXV series |
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From DS922 datasheet:
| From DS922 datasheet:
| This was used on the previous TXI digital board.
| This was originally used in this design before the schematic review.
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|
Altium 365 project folder: https://stanford-linear-accelerator-center.365.altium.com/designs/folder-077F97F3-88BC-43E1-A2A7-66F200D82CFA
Digital Board GT-Readout-Platform-digital | Analog Board GT-Readout-Platform-analog | Carrier Template Board GT-Readout-Platform-carrier-template | |
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3D view | |||
Description | Digital board for the GT Readout Platform with FPGA and optical transceivers | Analog board for the GT Readout Platform with power supplies, monitoring and calibration circuit for the ASIC carrier board that plugs into it | Template board for ASICs that plugs into the analog board in the GT Readout Platform |
Altium 365 project | |||
Board tracking |
Multi-board project | Carrier Board | |
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3D view | ||
Description | A configuration of the GT Readout Platform with a 2x2 carrier of ePixUHR100k ASICs. | Carrier board for a 2x2 configuration of ePixUHR100k ASICs for use with the GT Readout Platform |
Altium 365 project | ||
Board tracking |
Multi-board project | Carrier Board | |
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3D view | ||
Description | A configuration of the GT Readout Platform with a 1x4 and 4x1 carrier of ePixUHR100k ASICs. | Carrier board for a 1x4 configuration of ePixUHR100k ASICs for use with the GT Readout Platform |
Altium 365 project | ||
Board tracking |
See HE project - SparkPix-S 1x4
The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.
Gliffy Diagram | ||||||
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UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575)
The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.
Gliffy Diagram | ||||||
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The carrier board contains the specific ASICs and any passive components that are needed.
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https://webench.ti.com/power-designer/switching-regulator
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title | General IOs for the 2x2(numbers based on ePixHR250M) |
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ePixUHR Signals (single ASIC)
N# Pins
Power Digital Signals
N# Pins
Digital Core Signals
N# Pins
P&CB Signals
N# Pins
Waveform/ ASIC Ctrl
5
LDO enables
7
Env. Monitors
7
Misce
24
Clk
2 (0 if also clk_matrix is sent via GT)
DCDC Syncs
2
Bias DAC
4
Spare
6
Slow Ctrl (SACI/Sugoi)
4
HS DAC
4
Digital Monitor
2
HS ADC
6+24+8 =38
Miscellan
5
Jitter Cleaner
12
Total
13
Total
9
Total
70
Total
30
TOTAL = 13 * 4(n.Asics) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP
Expand | ||
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For single ended → check the electrical specification |
Component
Product number
Board
Operation Voltage
Power consumption
N# I/O needed
Needs substitution?
Quad SPI Configuration Memory
MT25QU01GBBB8E12
Digital
1.8 V
Max 50 mA
4
No, we can use HR pins
EEPROM
???
Digital
???
???
???
JTAG
Digital
1.8/1.5/1.2 V
4
No, we can either use HR or go to 1.2V
Analog Monitor (SlowADC) ADC
ADS1217
Both (key at the analog board, optional at the digital board)
AVDD =3V, DVDD =1.8V
< 1 mA
7
Maybe. The datasheet guarantees operation for digital down to 2.7V, in HR250 was put at 1.8. Check if it is fine!
Analog Monitor MUX (x5)
MAX4734
may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...)
AVDD =3V
< 1 uA
None
They are controlled by the ADC
Humidity sensor
HIH_5031_001
Analog
3 V
None
No
Thermistor
NTC_NHQM103B375T10
None
No
Oscillators
•371 MHz XLL726371.428571I
•156 MHz 536FB156M250DG
•48 MHz CX3225SB48000D0FPJC1
Digital
2.5 V
Both 1.8 V and 2.5V solutions can be found depending on the voltage we want to use
Clock Fanout
SI53340-B-GM
Digital
2.5 / 1.8V
Now is 2.5, probably can be switch to 1.8, but since its AC-coupled should not matter. Check if we can remove the 2.5 LDO
Clock Jitter cleaner
SI5345_64QFN
Digital
VDD = 3.3V, DVDD =1.8V
12 + n. clks
Programmable Oscillator
LMK61E2
Digital
3.3 V
Used?
High Speed ADC
AD9249
Analog
1.8 V
Max 58mW/channel:
58*12 = 700mW
38
No
ADC_MON_VCM Buffer
AD8607_MSO8
Analog
1.8V
Bias DAC (HV Ring)
MAX5443 (DAC) +
MAX14611 (Level Shifter) +
REF192GS (Voltage reference)
Analog
3.0 V (VCCA)
4
Maybe? Will the sensors have an HV ring?
ASIC clk fanout
SI53340-B-GM
Probably not needed
HS DAC (Vcalib_p)
MAX5719A(DAC)+
MAX14611 (Level Shifter) +
OP213 (Buffer)
MAX6126A41+(Vref)
Analog
5V
Why was this chosen? Do we need the 5 V supply?
HS DAC (Vcalib_p)
AD5541A (DAC)
+OPA2626(Buffer)
+ADR360B(Vref)
VDD = 3/3.3V
VLogic = 1.8V
Vref = 2V
Level Shifter for Power controllers
MAX3378EETD (x2)
MAX3373E_SOT23_8 (x1)
to be defined
1.8V -> 3.3V
Serial number
DS2411R
Carrier, analog and digital boards
Digital: 3.3V
Analog: 3.3V?
Carrier: 2.5V?
Line Equalizer
(check the one used for cryo)
Analog
Gliffy Diagram | ||||||||
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Gliffy Diagram | ||||||||
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The photo below shows the current cooling block designs (straight and angled), which is for a 30x6 SEAM/SEAF connector between analog and digital board.
The screenshot below shows that a 40x8 SEAM/SEAF connector can fit by extending the cutout in the cooling block without interfering with the pipe. Orange lines are the outline of the cooling block and the pipes in it.
The new connector is 10*1.27 = 12.7 mm longer.
The components listed in the expansion box below are currently missing from the SLAC Altium library located on OneDrive (Altium_Yee_lib).
Expand |
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DC/DC
Connectors:
FPGA:
Thermistor, humidity:
Analog:
ID:
Memory:
Oscillator/clock:
Level-shifters:
Gigabit transceiver:
Passives:
|
The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.
Gliffy Diagram | ||||||
---|---|---|---|---|---|---|
|
UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575)
The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between the two high-density connectors.
Gliffy Diagram | ||||||
---|---|---|---|---|---|---|
|
The carrier board contains the specific ASICs and any passive components that are needed.