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Clicking on the Down Converter Front Panel Image and the Up Converter Front Panel Image shows the up converters and the down converters AMC card front panel images respectively, and are shown in Figure 3. Each port on the AMC card front panel has a name and may be referenced in the DaqMux output stream selection drop box.
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Clicking on the Down Converter Front Panel Image and the Up Converter Front Panel Image shows the up converters and the down converters AMC card front panel images respectively, and are shown in Figure 3. Each port on the AMC card front panel has a name and may be referenced in the DaqMux output stream selection drop box.
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The DaqMux output stream selection dropbox example is shown in Figure 4.
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The DaqMux output stream selection dropbox example is shown in Figure 4.
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All possible options of the DaqMux input and their descriptions are summarized in Table 1.
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The Stream settings tab on the other hand contains channel specific settings, and are described as follows (Similarly, if the configuration name in GUI differs from the control register/PV Alias, the mapped Alias is shown between parenthesis):
The Stream settings tab on the other hand contains channel specific settings, and are described as follows:
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Register name |
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Word address | Access | Bits | PV Name | Alias | Description | |
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Control | 0x0 | RW | 0 | SW Trigger Enable | Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again. | |
1 | ${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRG | Cascade Trigger enable | Enabling/disabling cascaded trigger
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2 | ${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARM | Auto Rearm HW Trigger | Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger
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3 | ${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRG | Arm HW Trigger | Arms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register. | |||
4 | ${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGST | Trigger Clear Status | Trigger status will be cleared (On the rising edge). | |||
5 | ${DEVICE}:DAQMUX${DAQMUX#}_DAQMODE | Daq Mode | Select the data acquisition mode ( Stream stops if Error occurs )
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6 | ${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADER | Packet Header Enable | Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only)
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7 | ${DEVICE}:DAQMUX${DAQMUX#}_FRZBUF | SW Freeze Buffer | Freezes all enabled circular buffers | |||
8 | ${DEVICE}:DAQMUX${DAQMUX#}_HWFRZ | HW Freeze Buffer Enable | Enabling/disabling hardware freeze buffer request
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Status | 0x1 | RO | 0 | Software Trigger Status | Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ). | |
1 | Cascade Trigger Status | Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ) | ||||
2 | HW Trigger Status | Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ) | ||||
3 | HW Trigger Armed Status | Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs ) | ||||
4 | Combined Trigger Status | Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] ) | ||||
5 | Freeze Buffers Status | Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] ) | ||||
Decimation | 0x2 | RW | 15:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIV | Decimation Rate Divisor | Sample rate divider (Decimator):
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DataSize | 0x3 | RW | ${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZE | Data Buffer Size | Number of 32-bit words to forward at each trigger (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header). | |
TimeStamp | 0x4 | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TS_NSEC | Timestamp[31:0] | Timestamp [31:0] - secPastEpoch |
0x5 | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TS_SEC | Timestamp[63:32] | Timestamp [63:32] - nsec | |
BSA | 0x6 | RO | 31:0 | bsa(0) | edefAvgDn | |
0x7 | 31:0 | bsa(1) | edefMinor | |||
0x8 | 31:0 | bsa(2) | edefMajor | |||
0x9 | 31:0 | bsa(3) | edefInit | |||
TrigCount | 0xA | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TRGCNT | Trigger Count | Counts valid data acquisition triggers |
DbgInputValid | 0xB | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALID | Debug Input Valid | All DaqMux AXI input streams valid signals |
DbgLinkReady | 0xC | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDY | Debug Link Ready | All DaqMux AXI input streams ready signals |
InputMuxSel | 0x10 | RW | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0 | Input Mux Select[0] | 0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) Test mode will output counter data |
0x11 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1 | Input Mux Select[1] | |||
0x12 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2 | Input Mux Select[2] | |||
0x13 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3 | Input Mux Select[3] | |||
0x14-0x1F | - | Not used | ||||
DaqStatus | 0x20-0x23 | RO | 0 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3) | Stream Pause | Debug flag: Raw diagnostic stream control pause (Waveform engine bufferDone signal. When |
an AXI frame is completely written to DRAM, this bit is set) | |||
1 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3) | Stream Ready | Debug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal) |
2 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3) | Stream Overflow | Debug flag: Raw diagnostic stream control Overflow (set to 0 in waveform engine) |
3 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3) | Stream Error | Debug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped) |
4 | ${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3) |
Data |
source ready | Debug signal: The |
data |
source is ready. If not, DaqMux sets error signal to 1 | |||
5 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3) | Stream Enable | Debug signal: Output stream enabled |
31:6 | ${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3) | Frame Count | Number of 4096 |
word frames sent | ||||
024-0x2F | Not used | |||
DataFormat | 0x30-0x33 | RW | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3) |
Sign |
Bit Position | Indicating sign extension point (all bits after sign bit will be overwritten with sign) | |||
5 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3) |
Data Width | Data width 32-bit or 16-bit
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6 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3) |
Sign enable | Signed/unsigned
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7 | ${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3) | Decimation Averaging Enable | Decimation Averaging
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${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQ | SW Trigger Pulse | A sequence setting Software Trigger Enable to 1 then 0 |
Legend:
Not in original requirements document | |
Not exported to EPICS |
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The DaqMux streams are routed to the DRAM on the application board, and are read using another series of components and exported to the software using the cpswDebugStreamAsynDriverConfigure IOC shell command of the ATCACommon EPICS module, which is out of the scope of this document. This module provides all stream information in format of PVs. The available exported PVs are shown in Table 3. As can be seen, this module exports the streams represented with STR (and no longer with DAQMUX). Usually the software engineer would keep the numbering the same and just changing the string to minimize confusion.
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PV name | Description |
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${DEVICE}:STR{DAQMUX#}:STREAM_TYPE(0-3) | The data type of the corresponding channel |
${DEVICE}:STR{DAQMUX#}:STREAM_SHORT${DATATYPE}(0-3) | The data stream of the corresponding channel on full speed of type ${DATATYPE} ∈ {SHORT, LONG, USHORT, ULONG, DOUBLE, FLOAT} |
${DEVICE}:STR{DAQMUX#}:STREAM_SLOWSHORTSLOW${DATATYPE}(0-3) | The data stream of the corresponding channel on reduced speed of type ${DATATYPE} ∈ {SHORT, LONG, USHORT, ULONG, DOUBLE, FLOAT} |