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The SIMs used here are designed to function as Phase Locked Loops (PLLs).  A PLL is an electronic circuit with a voltage controlled oscillator (VCO) that constantly adjusts to match the frequency of an input signal.  PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a noisy communications channel.  The main purpose of a PLL is to synchronize the output signal with a reference signal.  It starts with estimating the phase difference between the input and reference signals.  By constantly adjusting the VCO voltage, a PLL reduces phase errors between output and input frequencies.  When the phase difference between these signals is zero, the system is said to be locked.  Besides synchronizing output and input reference frequencies (i.e. lock the phases), a PLL also helps achieve frequency lock in a circuit.

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(Diagram above by Bo Hong)

For the purpose of Linac Locking, the 476MHz RF signal is the VCO output located in the Resynchronization Chassis.  To generate this, an 11.5MHz VCO input and other RF signals from the Master Oscillator rack (i.e. 162.5MHz and 650MHz) are manipulated in such a way that a 476MHz RF signal is produced.  The SIM PLL crates ensure that the 11.5MHz and 476MHz PLL output signals that are routed back to the Resynchronization chassis Chassis remain locked in phase and frequency with their respective input reference signals (also taken from the Resynchronization chassis. (Diagram below by Bo Hong)Image RemovedChassis).  Further down the RF path, the 476MHz signal will be transported to Sector-2 via a (~1Km long) fiber cable and will be designated as the Main Drive Line (MDL) for PCAV, XTCAV and more.

The PLL IOCs expose the SIM PLL FPGA registers to EPICS records, which can then be monitored and/or tuned in order to ultimately achieve a lock in both phase and frequency for the 11.5MHz and 476MHz RF signals.

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PV name for LCLS2 Master Source

New Displays

Displays in both Dev and Production exist for the control of the PLLs.

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To access and launch the display dashboard GUI in either Dev or Production, follow the steps outlined below. log onto the appropriate host (Dev ==> lcls-dev3, Production ==>  lcls-srv01) and then run the command mslk_dashboard:

[softegr@lcls-srv01 skoufis]$ mslk_dashboard
lcls-srv01
[2024-03-18 15:26:22,275] [INFO    ] - Using PyDM via SSH. Reverting to Software Rendering.
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Upon running the command successfully, the following display is invoked.  Click on the 11.5 MHz Loop and/or 476 MHz Loop buttons to launch the respective displays.

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Old Displays

Note that the preferred display is the newer display shown above.  However, we include instructions on how to launch directly the old displays if needed.

Dev

To access and launch the display in Dev, follow the steps outlined below.

For the 11.5MHz PLL GUI:

(base) skoufis@aird-b50-srv01  (master) $ cd $EPICS_IOCS/sioc-b084-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/ 
(base) skoufis@aird-b50-srv01  (master) $ ./prl115_b084_screen

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[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl115_screenprl115_screen

This should bring up the following screen:

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For the 476MHz PLL GUI:

[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms08/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl476_screen

This screen is identical to the one before:

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Deliverables

The released software will be made available in the main IOC release area post-deployment (Dev: /afs/slac/g/lcls/epics/iocTop/masterSource/, Production:/usr/local/lcls/epics/iocTop/masterSource/).  See below for the specific repositories and tags.

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See firmware release details below.

References