...

Term	Description
ATCA	Advanced Telecommunications Computing Architecture
CPU	Central Processing Unit
EPICS	Experimental Physics and Industrial Control System
FPGA	Field Programmable Gate Array
IOC	Input Output Controller
MDL	Main Drive Line
PLL	Phase Locked Loop
RF	Radio Frequency
SHM	Shelf Manager
VCO	Voltage Controlled Oscillator

https://www.thinksrs.com/products/sim.html

Image Added

The SIMs used here are designed to function as Phase Locked Loops (PLLs). A PLL is an electronic circuit with a voltage controlled oscillator (VCO) that constantly adjusts to match the frequency of an input signal. PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a noisy communications channel. The main purpose of a PLL is to synchronize the output signal with a reference signal. It starts with estimating the phase difference between the input and reference signals. By constantly adjusting the VCO voltage, a PLL reduces phase errors between output and input frequencies. When the phase difference between these signals is zero, the system is said to be locked. Besides synchronizing output and input reference frequencies (i.e. lock the phases), a PLL also helps achieve frequency lock in a circuit.

DHCP Configuration

The PLL instrumentation gets assigned IP addresses in order for the IOC to interface with the PLL FPGA registers. See below for the IP addresses assigned to the 11.5MHz and 476MHz PLLs.

Image Added

(Diagram above by Bo Hong)

For the purpose of Linac Locking, the 476MHz RF signal is the VCO output located in the Resynchronization Chassis. To generate this, an 11.5MHz VCO input and other RF signals from the Master Oscillator rack (i.e. 162.5MHz and 650MHz) are manipulated in such a way that a 476MHz RF signal is produced. The SIM crates ensure that the 11.5MHz and 476MHz PLL output signals that are routed back to the Resynchronization Chassis remain locked in phase and frequency with their respective reference signals (also taken from the Resynchronization Chassis). Further down the RF path, the 476MHz signal will be transported to Sector-2 via a (~1Km long) fiber cable and will be designated as the Main Drive Line (MDL) for PCAV, XTCAV and more.

The PLL IOCs expose the SIM PLL FPGA registers to EPICS records, which can then be monitored and/or tuned to ultimately achieve a lock in phase and frequency for the 11.5MHz and 476MHz RF signals.

DHCP Configuration

The PLL instrumentation gets assigned IP addresses in order for the IOC to interface with the PLL FPGA registers. See below for the IP addresses assigned to the 11.5MHz and 476MHz PLLs.

Code Block

language	bash

[softegr@lcls-srv01 skoufis]$ cat $EPICS_IOCS/cpu-sys0-sp01/iocSpecificRelease/cpuBoot/lcls/cpu-sys0-sp01/dhcpd.conf 

...

##########################
#  Linac Locking Project #
##########################

# SN = 17
# 11.5MHz PLL control in L2KG02-27
# digital

Code Block

language	bash

[softegr@lcls-srv01 skoufis]$ cat $EPICS_IOCS/cpu-sys0-sp01/iocSpecificRelease/cpuBoot/lcls/cpu-sys0-sp01/dhcpd.conf 

...

##########################
#  Linac Locking Project #
##########################

# SN = 17
# 11.5MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim17 {
  hardware ethernet 08:00:56:00:46:F9;
  fixed-address 192.168.1.17;
}

# SN = 18
# 476MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim18 {
    hardware ethernet 08:00:56:00:46:FB;
    fixed-address 192.168.1.18;
}

...

Code Block

language	bash

(base) skoufis@aird-b50-srv01  (master) $ cat archive/sioc-sys0-ms08.archive
PRL:SYS0:08:PHASESHIFT_RBV                    1       monitor
PRL:SYS0:08:LOOPFILTER_RESET_RBV              1       monitor
PRL:SYS0:08:LED                               1       monitor
PRL:SYS0:08:PHASEERR1                         1       monitor
PRL:SYS0:08:PHASEERR2                         1       monitor
PRL:SYS0:08:LOCK                              1       monitor
PRL:SYS0:08:INPUTMUX_RBV                      1       monitor
PRL:SYS0:08:W0SCALE_RBV                       1       monitor
PRL:SYS0:08:W1_RBV                            1       monitor
PRL:SYS0:08:PRAMPSLOPE_RBV                    1       monitor
PRL:SYS0:08:ADCAMP0_RBV                       1       monitor
PRL:SYS0:08:ADCAMP1_RBV                       1       monitor
PRL:SYS0:08:LOCKDISABLE_RBV                   1       monitor
PRL:SYS0:08:LOCKRESET_RBV                     1       monitor
PRL:SYS0:08:LED_ADCAMPL                       1       monitor
PRL:SYS0:08:LED_ERROR                         1       monitor
PRL:SYS0:08:LED_LOCK                          1       monitor
PRL:SYS0:08:UNLOCKCNT                         1       monitor
PRL:SYS0:08:TXFRAMERATE                       1       monitor
PRL:SYS0:08:SIMVER                            1       monitor
PRL:SYS0:08:FLTB:POSTTRIGDLY                  1       monitor
PRL:SYS0:08:FLTB:LOGRATE                      1       monitor
PRL:SYS0:08:ODMB0:POSTTRIGDLY                 1       monitor
PRL:SYS0:08:ODMB0:LOGRATE                     1       monitor
PRL:SYS0:08:ODMB1:POSTTRIGDLY                 1       monitor
PRL:SYS0:08:ODMB1:LOGRATE                     1       monitor
PRL:SYS0:08:PHASESHIFT                        1       monitor
PRL:SYS0:08:W0SCALE                           1       monitor
PRL:SYS0:08:W1                                1       monitor
PRL:SYS0:08:PRAMPSLOPE                        1       monitor
PRL:SYS0:08:LOCKDISABLE                       1       monitor
PRL:SYS0:08:LOCKRESET                         1       monitor
PRL:SYS0:08:LOOPFILTER_RESET                  1       monitor
PRL:SYS0:08:INPUTMUX                          1       monitor
PRL:SYS0:08:RESETUNLOCKCNT                    1       monitor
PRL:SYS0:08:LOOPFILTERGAIN_OUT                1       monitor
PRL:SYS0:08:LOOPFILTERGAIN                    1       monitor
PRL:SYS0:08:VCOGAIN                           1       monitor
PRL:SYS0:08:VCOGAIN_OUT                       1       monitor
PRL:SYS0:08:EFMULTGAIN                        1       monitor
PRL:SYS0:08:EFMULTGAIN_OUT                    1       monitor
SIM08:M:PRLMST:PhaseShift:St       1000    monitor
SIM08:M:PRLMST:LoopReset:St        1000    monitor
SIM08:M:PRLMST:LED:Rd              1000    monitor
SIM08:M:PRLMST:Input_MUX:St        1000    monitor
SIM08:M:PRLMST:w0_scale:St         1000    monitor
SIM08:M:PRLMST:w1:St               1000    monitor
SIM08:M:PRLMST:Phase_ramp_gain:St  1000    monitor
SIM08:M:PRLMST:LockDisable:St      1000    monitor
SIM08:M:PRLMST:StateReset:St       1000    monitor

# autosave Save/Restore Archive template
# Format:
# <PVNAME> <PERIOD> [ monitor ]

# Archive each status change
SIOC:SYS0:MS08:SR_rebootStatus 1 monitor
SIOC:SYS0:MS08:SR_status 1 monitor
SIOC:SYS0:MS08:SR_rebootStatusStr 1 monitor
SIOC:SYS0:MS08:SR_statusStr 1 monitor
SIOC:SYS0:MS08:SR_0_Status 1 monitor
SIOC:SYS0:MS08:SR_0_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_1_Status 1 monitor
SIOC:SYS0:MS08:SR_1_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_2_Status 1 monitor
SIOC:SYS0:MS08:SR_2_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_3_Status 1 monitor
SIOC:SYS0:MS08:SR_3_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_4_Status 1 monitor
SIOC:SYS0:MS08:SR_4_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_5_Status 1 monitor
SIOC:SYS0:MS08:SR_5_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_6_Status 1 monitor
SIOC:SYS0:MS08:SR_6_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_7_Status 1 monitor
SIOC:SYS0:MS08:SR_7_StatusStr 1 monitor
SIOC:SYS0:MS08:SR_0_State 1 monitor
SIOC:SYS0:MS08:SR_1_State 1 monitor
SIOC:SYS0:MS08:SR_2_State 1 monitor
SIOC:SYS0:MS08:SR_3_State 1 monitor
SIOC:SYS0:MS08:SR_4_State 1 monitor
SIOC:SYS0:MS08:SR_5_State 1 monitor
SIOC:SYS0:MS08:SR_6_State 1 monitor
SIOC:SYS0:MS08:SR_7_State 1 monitor

# Archive these values only when they change
SIOC:SYS0:MS08:SR_recentlyStr 30 monitor
SIOC:SYS0:MS08:SR_rebootTime 30 monitor
SIOC:SYS0:MS08:SR_0_Name 30 monitor
SIOC:SYS0:MS08:SR_1_Name 30 monitor
SIOC:SYS0:MS08:SR_2_Name 30 monitor
SIOC:SYS0:MS08:SR_3_Name 30 monitor
SIOC:SYS0:MS08:SR_4_Name 30 monitor
SIOC:SYS0:MS08:SR_5_Name 30 monitor
SIOC:SYS0:MS08:SR_6_Name 30 monitor
SIOC:SYS0:MS08:SR_7_Name 30 monitor

# Archive these values at the specified rate
SIOC:SYS0:MS08:SR_heartbeat 30
SIOC:SYS0:MS08:SR_0_Time 30
SIOC:SYS0:MS08:SR_1_Time 30
SIOC:SYS0:MS08:SR_2_Time 30
SIOC:SYS0:MS08:SR_3_Time 30
SIOC:SYS0:MS08:SR_4_Time 30
SIOC:SYS0:MS08:SR_5_Time 30
SIOC:SYS0:MS08:SR_6_Time 30
SIOC:SYS0:MS08:SR_7_Time 30

# archive_iocAdmin Archive template
# Format:
# <PVNAME> <PERIOD> [ monitor ]

# Archive these values only when they change
SIOC:SYS0:MS08:APP_DIR 30 monitor 
SIOC:SYS0:MS08:APP_DIR1 30 monitor 
SIOC:SYS0:MS08:APP_DIR2 30 monitor 
SIOC:SYS0:MS08:CA_CLNT_CNT 1 monitor 
SIOC:SYS0:MS08:CA_CONN_CNT 1 monitor 
SIOC:SYS0:MS08:EPICS_VERS 30 monitor
SIOC:SYS0:MS08:FD_CNT 1 monitor 
SIOC:SYS0:MS08:FD_FREE 1 monitor 
SIOC:SYS0:MS08:FD_MAX 1 monitor 
SIOC:SYS0:MS08:HOSTNAME 30 monitor
SIOC:SYS0:MS08:KERNEL_VERS 30 monitor
SIOC:SYS0:MS08:RECORD_CNT 10 monitor
SIOC:SYS0:MS08:START_CNT 30 monitor
SIOC:SYS0:MS08:STARTTOD 30 monitor
SIOC:SYS0:MS08:ST_SCRIPT 30 monitor 
SIOC:SYS0:MS08:ST_SCRIPT1 30 monitor 
SIOC:SYS0:MS08:ST_SCRIPT2 30 monitor 
SIOC:SYS0:MS08:SUSP_TASK_CNT 30 monitor 
SIOC:SYS0:MS08:ST_SCRIPT2 30 monitor SYSRESET 30 monitor 

# Archive these values at the specified rate
SIOC:SYS0:MS08:SYS_CPU_LOAD 10
SIOC:SYS0:MS08:LOAD 10 
SIOC:SYS0:MS08:MEM_BLK_FREE 10 
SIOC:SYS0:MS08:MEM_FREE 10 
SIOC:SYS0:MS08:SUSPMEM_TASK_CNT 30 monitor USED 10 
SIOC:SYS0:MS08:SYSRESET 30 monitor 

# Archive these values at the specified rate
SIOC:SYS0:MS08:SYS_CPU_LOAD 10
SIOC:SYS0:MS08:LOAD 10 
SIOC:SYS0:MS08:MEM_BLK_FREE 10 
SIOC:SYS0:MS08:MEM_FREE 10 
SIOC:SYS0:MS08:MEM_USED 10 
SIOC:SYS0:MS08:UPTIME 3600

IOC initialization

Initialize the IOC and logging capability.

UPTIME 3600

IOC initialization

Initialize the IOC and logging capability.

Code Block

language	bash

# ===========================================
#               IOC INIT
# ===========================================
iocInit()

Code Block

language	bash

# ===========================================
#               IOC INITCAPUTLOG
# ===========================================
iocInit()


# Turn on caPutLogging:
# Log values only on change to the iocLogServer:
caPutLogInit("${EPICS_CA_PUT_LOG_ADDR}")
caPutLogShow(2)

Autosave start

Start the autosave process.

Code Block

language	bash

# ===========================================
#               CAPUTLOGAUTOSAVE
# ===========================================
# Turn on caPutLogging:
# Log values only on change to the iocLogServer:
caPutLogInit("${EPICS_CA_PUT_LOG_ADDR}")
caPutLogShow(2)

Autosave start

Autosave start
< $(TOP)/iocBoot/common/autosave_start.cmd

EPICS Records

A complete list of the PLL IOC Process Variables (PVs) can be found in the page linked below, Look for Section PLL Loop for L0-L1 PRL (L0-L1 VCO Control).

PV name for LCLS2 Master Source

New Displays

Displays in both Dev and Production exist for the control of the PLLs.

To launch the dashboard GUI in either Dev or Production, log onto the appropriate host (Dev ==> lcls-dev3, Production ==> lcls-srv01) and then run the command mslk_dashboard:Start the autosave process.

Code Block

language	bash

# ===========================================
#               AUTOSAVE
# ===========================================
# Autosave start
< $(TOP)/iocBoot/common/autosave_start.cmd

EPICS Records

A complete list of the PLL IOC Process Variables (PVs) can be found in the page linked below, Look for Section PLL Loop for L0-L1 PRL (L0-L1 VCO Control).

PV name for LCLS2 Master Source

Displays

[softegr@lcls-srv01 skoufis]$ mslk_dashboard
lcls-srv01
[2024-03-18 15:26:22,275] [INFO    ] - Using PyDM via SSH. Reverting to Software Rendering.
...

Upon running the command successfully, the following display is invoked. Click on the 11.5 MHz Loop and/or 476 MHz Loop buttons to launch the respective displays.

Image Added

Old Displays

Note that the preferred display is the newer display shown above. However, we include instructions on how to launch directly the old displays if neededDisplays in both Dev and Production exist for the control of the PLLs.

Dev

To access and launch the display in Dev, follow the steps outlined below.

For the 11.5MHz PLL GUI:

Code Block

language	bash

(base) skoufis@aird-b50-srv01  (master) $ cd $EPICS_IOCS/sioc-b084-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/ 
(base) skoufis@aird-b50-srv01  (master) $ ./prl115_b084_screen

...

Code Block

language	bash

[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms07/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl115_screenprl115_screen

This should bring up the following screen:

Image Added

For the 476MHz PLL GUI:

Code Block

language	bash

[softegr@lcls-srv01 skoufis]$ cd $EPICS_IOCS/sioc-sys0-ms08/iocSpecificRelease/masterSourceApp/srcDisplay/
[softegr@lcls-srv01 skoufis]$ ./prl476_screen

This screen is identical to the one before:

Image Added

Deliverables

The released software will be made available in the main IOC release area post-deployment (Dev: /afs/slac/g/lcls/epics/iocTop/masterSource/, Production:/usr/local/lcls/epics/iocTop/masterSource/). See below for the specific repositories and tags.

...

See firmware release details below.

Repository

Image
AFS Path	PLL Version
Gen1Lcls2PrlMaster-0x02020000-20221211144144-charliex-ad16e63.mcs	/u/cd/charliex/users/charliex/LCLS_PRL/lcls2-prl/firmware/targets/Gen1Lcls2PrlMaster/images	11.5MHz PLL
Gen1Lcls2PrlMaster-0x02020000-20230313162512-charliex-ca8aca6.mcs	/u/cd/charliex/users/charliex/LCLS_PRL/lcls2-prl/firmware/targets/Gen1Lcls2PrlMaster/images	476MHz PLL

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Old Version 33

New Version Current

Key

DHCP Configuration

DHCP Configuration

IOC initialization

IOC initialization

Autosave start

Autosave start

EPICS Records

New Displays

EPICS Records

Displays

Old Displays

Dev

Deliverables

References

Space shortcuts

Confluence Content

Child pages

Page History

Versions Compared

Old Version 33

New Version Current

Key

DHCP Configuration

DHCP Configuration

IOC initialization

IOC initialization

Autosave start

Autosave start

EPICS Records

New Displays

EPICS Records

Displays

Old Displays

Dev

Deliverables

References