This manual serves as an end-user manual to configure and use the DaqMux through the IOC.
Overview
The DaqMux sub-system is shown in Figure 1. The DaqMux component of the FPGA in the application board of the ATCA allows the user to choose to stream upto up to four streams to the software (IOC) of the input streams routed to the DaqMux. All ATCA projects are configured to have two DaqMuxes, one associated with each AMC daughter board, summing a total of 8 streams routed to software. Each of the two DaqMux has 20 streams of data routed to its input. Acquisition can be either continuous, single, or single many times. In all three cases a trigger is needed. In the continuous case (i.e. continuous mode), at every trigger, the DaqMux acquires a number of configured bytes (i.e. Frame count) and sends them up to software. In single acquisition (trigger mode), the DaqMux is armed only once, and a number of configured words (i.e. Frame count) is sent to software with or without a header. Finally, single many-times-acquisition is just a sub-case of single acquisitions, however; auto re-arm is enabled, and every time there is a trigger, a number of configured words (i.e. Frame count) is sent to software with or without a header.
The DaqMux functionality can be summarized as follows:
- Multiplex up to 4 streams and send forward (to software)
- Streams can be acquired continuously every time a trigger arrives in continuous mode, or only once upon trigger with or without header (meta data) in trigger mode, or many times with or without header (meta data) in trigger mode when auto re-arm is enabled
- Possibility of cascading trigger of DaqMux blocks
- Pause streaming by not overwriting buffers (freeze functionality), therefore nothing is forwarded to software
- Down sampling and averaging
Figure 1: DaqMux connectivity overview
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DaqMux screens
The Graphical user interface of a DaqMux is shown in Figure 2 of chosen data from each AMC daughter board to the IOC. Each application card is configured to have 2 DaqMuxes; one for each AMC daughter board. The main graphical user interface for configuring the DaqMux is quite simple and masks a lot of the DaqMux configurations. It only allows the user to choose perform the basicfollowing:
- Choose the source of each of the 4 streams of each DaqMux
...
- Stimulate a software trigger in any of the two DaqMuxes
...
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Figure 1: DaqMux Graphical user interface
....
Updated table extracted from the DaqMux.yaml (incomplete)
- Open complete DaqMux settings
- View the AMC Up Converter and Down Converter card front panel image
- There are several variations of the AMC cards (Not just the up and down converters used for LLRF). Here is a list of cards and the managing entities
Figure 2: DaqMux graphical user interface
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Clicking on the Down Converter Front Panel Image and the Up Converter Front Panel Image shows the up converters and the down converters AMC card front panel images respectively, and are shown in Figure 3. Each port on the AMC card front panel has a name and may be referenced in the DaqMux output stream selection drop box.
Figure 3: Up and down converter AMC cards front panel images
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The DaqMux output stream selection dropbox example is shown in Figure 4.
Figure 4: DaqMux output stream selection dropbox for Down converter (Left) and Up converter (Right)
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The syntax used in the DaqMux output stream selection dropbox is one of the following options:
- 3 parts → X : Y : Z
- X: DaqMux input number
- Y: Source of the DaqMux stream
- Z: ADC/DAC where that source is connected - intermediate path (Not really important for end users)
- 2 parts → X : Y
- X: DaqMux input number
- Y: It can be
- a source generated from
- the application side (i.e. DBG/Debug, Test)
- Unused DAC/ADC port
- Disabled
- Test (Simple counter data)
All possible options of the DaqMux input and their descriptions are summarized in Table 1.
Table 1: Possible combinations in the stream channel selection drop down combo boxSource | Description |
---|
${MuxIn#} : Test | Test pattern stream (simple counter data) |
${MuxIn#} : Disable | Disable stream |
${MuxIn#} : ADC${ADC#} | ADC Source not connected |
${MuxIn#} : DAC${DAC#} | DAC Destination not connected |
${MuxIn#} : DBG${DBG#} | Debug streams - application specific and used for debugging (e.g. not used in GMD firmware) |
${MuxIn#} : RF IN ${RF#} : ADC${ADC#} FP | Stream data coming through AMC front panel physical port RF IN ${RF#} through ADC${ADC#} |
${MuxIn#} : RF OUT MON : ADC${ADC#} FP | Stream data coming through AMC front panel physical port RF OUT MON through ADC${ADC#} |
${MuxIn#} : DC IN ${DC#} : ADC${ADC#} FP | Stream data coming through AMC front panel physical port DC IN ${DC#} through ADC${ADC#} |
${MuxIn#} : TRIG MON : ADC${ADC#} (FP) | Stream data coming through AMC front panel physical port TRIG MON through ADC${ADC#} |
${MuxIn#} : CLK PLL DAC : DAC${DAC#} | Stream the applied voltage to the voltage controlled oscillator transmitted through DAC${DAC#} |
${MuxIn#} : LO PLL DAC : DAC${DAC#} | Stream the applied LO signal mixed with RF sinal to get an IF signal transmitted through DAC${DAC#}. This is specific to the LLRF applcation |
${MuxIn#} : DAC OUT : DAC${DAC#} (FP) | Stream data coming out through AMC front panel physical port DAC OUT through DAC${DAC#} |
${MuxIn#} : RF OUT : DAC${DAC#} (FP) | Stream data coming out through AMC front panel physical port RF OUT through DAC${DAC#} |
DaqMux Settings setup
The DaqMux settings setup page allows the user to fine control the DaqMux by reading and writing to and from the DaqMux registers and some CPSW sequencers (program sequences of writings to a register). The DaqMux settings setup GUI is shown in Figure 5.
Figure 5: DaqMux settings setup GUI
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The DaqMux settings setup contains 3 tabs:
- DaqMux Settings : Contains general settings to ocnfigure the DaqMux
- Waveform Engine Settings (Next component in the data streaming pipeline to server - out of the scope of this document)
- Stream Settings : Contains channel specific settings (one for each of the 4 channels)
The possible functionalities that can be performed using the DaqMux settings tab are as follows: (Note if the configuration name in GUI differs from the control register Alias, the mapped Alias is shown between parenthesis)
- Freeze buffer (SW Freeze Buffer): If enabled, freezes all enabled circular buffers in firmware, hence all new data is discarded in firmware and software does not see new data
- Trigger count: Counts valid data acquisition triggers.
- Arm hardware trigger (Arm HW Trigger): Arm the trigger and wait for a trigger signal to arrive. Frame acquisition starts after trigger arrival and trigger is dis-armed
- Cascaded Trigger (Cascade Trigger enable) : Enable / Disable cascaded trigger between DaqMux module
- Auto re-arm (Auto Rearm HW Trigger): In trigger mode, once the acquisition finished, a new trigger will start a new acquisition automatically
- Daq Mode (DAQ Mode): Chose the acquisition mode (Continuous or Trigger mode)
- Packet Header (Packet Header Enable): Enable a 14-byte header containing information and a snapshot of the DaqMux configurations that is prepended to the acquired frame
- Hardware Freeze (HW Freeze Buffer Enable): Enable the use of the hardware freeze buffer input signal of the DaqMux
- Decimation rate divisor: Defines new down sampled rate
- Buffer size (Data Buffer Size) : Number of 32-bit words to be acquired including header if enabled
- Debug Input Valid : All DaqMux AXI input streams valid signals concatenated together (Debug)
- Debug link Ready: All DaqMux AXI input streams ready signals concatenated together (Debug)
- Time stamp (Timestamp[31:0] and Timestamp[63:32]) : The time stamp read from the timing core upon at trigger formatted in nano seconds (left) and seconds (right)
The Stream settings tab on the other hand contains channel specific settings, and are described as follows (Similarly, if the configuration name in GUI differs from the control register/PV Alias, the mapped Alias is shown between parenthesis):
- Trigger Daq (SW Trigger Pulse) : Sends a pulse to the software trigger enable register to stimulate an acquisition
- Stream Pause : Debug - set when frame is written to DRAM
- Stream Ready : Debug - Denote that the waveform engine is ready to forward data to software (set when waveform engine FIFO master input ready signal is set)
- Stream Overflow : Debug - denote overflow, however not used (set to 0 in waveform engine)
- Stream Error : Debug - Denote error during last acquisition
- Input Data Valid : Debug - Denoting that the incoming data is valid
- Stream Enabled : Debug - Denote that output stream in enabled
- Frame count (Frame Count) : Number of frames forwarded
- Format Sign Width (Sign Bit Position) : Position of the sign bit given that the first bit number is 0.
- Format Data Width (Data Width) : choose 32 (0) or 16 bits (1)
- Format Sign (Sign Enable): Enable sign (1) or not (0)
- Decimation (Decimation Averaging Enable): set if averaging is enabled
DaqMux register & PV description
A full list of all PVs and their Register mapping and description can be seen in Table 2. This table was extracted from the firmware YAML file of the DaqMux. Registers with a blank PV name are not exported to EPICS. PVs with not register names are generated in CPSW libraries, and eventually control registers by applying a sequence of values to them.
Table 2: Full list of Register name to PV mapping with functionality descriptionRegister name | Word address |
---|
Register name | AddressSub-nameAlias | Description |
---|
Control | 0x0 | RW | 0 |
Software
| SW Trigger Enable | Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again. |
1 | ${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRG | Cascade |
Sw maskMask for enablingEnabling/disabling cascaded trigger |
Disabled ( Sw ignored) Enabled |
2 | ${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARM | Auto Rearm |
Hw Mask for enablingEnabling/disabling hardware automatic trigger. If disabled it has to be rearmed by |
ArmHwTrigger. Arm Hw Trigger - '0' - Disabled (has to be armed with bit3 otherwise disabled)
|
3 |
bit3: Arm Hardware Trigger (Arms the ${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRG | Arm HW Trigger | Arms the hardware trigger on rising edge |
). After trigger occurs the trigger has to be rearmed using this register.
|
4 |
bit4: Clear status${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGST | Trigger Clear Status | Trigger status will be cleared (On the rising edge). |
5 |
bit5: DAQ Mode
${DEVICE}:DAQMUX${DAQMUX#}_DAQMODE | Daq Mode | Select the data acquisition mode ( Stream stops if Error occurs ) |
Triggered - Trigger mode - Normal DAQ mode
|
- - Has to be triggered to start
|
(Other reqs. to start: Enabled, dataValid, tReady, pause). - Stream stops if Error occurs.- - '1' - Continuous mode - The data is framed and continuously streamed out after enabled.
|
- Has to be triggered to start (Other reqs. to start: Enabled, dataValid, tReady, pause).
- (Still requires a trigger to start)
|
- Disable the stream to stop
|
.- Freeze buffers inserts flag into the tUser bit at tLast
- Stream stops if Error occurs.
6 | bit6: |
6 | ${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADER | Packet Header Enable |
Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only) - '0' - Disabled
- '1' - Enabled
|
7 |
bit7: Software freeze buffer (Freezes ${DEVICE}:DAQMUX${DAQMUX#}_FRZBUF | SW Freeze Buffer | Freezes all enabled circular buffers |
)bit8: Hardware freeze buffer mask${DEVICE}:DAQMUX${DAQMUX#}_HWFRZ | HW Freeze Buffer Enable | Enabling/disabling hardware freeze buffer request |
Status | 0x1 | RO |
bit0: | 0 |
| Software Trigger Status | Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control |
())bit1: ] ). |
1 |
| Cascade Trigger Status | Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control |
())bit2: ] ) |
2 |
| HW Trigger Status | Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control |
())bit3: ] ) |
3 |
| HW Trigger Armed Status | Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control |
() Hw hardware trigger occurs ) |
bit4: |
4 |
| Combined Trigger Status | Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control |
(bit5: ))] ) |
5 |
| Freeze Buffers Status |
Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control |
()bit -0 :0 | ${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIV | Decimation Rate Divisor | Sample rate divider (Decimator): |
Only - Averaging Enabled: (powers of two
|
allowed if Averaging is enabled (DataFormat(7) = '1': 2^15)Comment: If only powers of two allowed: why not encode this way? 0..16 (bit 4..0)
A: We will also have an option to disable averaging (Steve needs data without averaging). If the Averaging will be disabled also other
decimation factors will be allowed DataFormat(7)
Comment: Do we need to set decimation per channel?
The samples will be averaged (running average filter with powers of 2 window size- 2^12)
- Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).
- Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).
|
DataSize | 0x3 | RW |
| ${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZE | Data |
buffer size. - Number of 32-bit words to forward at each trigger (if enabled header will be included in the first 14 words of data). |
- Minimum size is 14 (the size of the header). |
Comment: Not sure this is more confusing than beneficial. IMO we should just use one of these.
A: Agree we will use number of 32-bit words as in old version.
|
TimeStamp | 0x4 | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TS_NSEC | Timestamp |
TimeStamp0x4RO | Timestamp [31:0] - secPastEpoch |
TimeStamp |
0x5 | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TS_SEC | Timestamp[63:32] |
0x5 | ROMultiplexer | 0x10-0x1F | RW | |
BSA | 0x6 | RO | 31:0 |
| bsa(0) | edefAvgDn |
0x7 | 31:0 |
| bsa(1) | edefMinor |
0x8 | 31:0 |
| bsa(2) | edefMajor |
0x9 | 31:0 |
| bsa(3) | edefInit |
TrigCount | 0xA | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TRGCNT | Trigger Count | Counts valid data acquisition triggers |
DbgInputValid | 0xB | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALID | Debug Input Valid | All DaqMux AXI input streams valid signals |
DbgLinkReady | 0xC | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDY | Debug Link Ready | All DaqMux AXI input streams ready signals |
InputMuxSel | 0x10 | RW | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0 | Input Mux Select[0] | 0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) |
Comment: Fw implementation wise I still think this format is optimal?
Will use enums in YAML to make it more user friendlyTest mode will output counter data |
0x11 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1 | Input Mux Select[1] |
0x12 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2 | Input Mux Select[2] |
0x13 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3 | Input Mux Select[3] |
0x14-0x1F |
| - | Not used |
|
DaqStatus | 0x20- |
0x2F0x2x: Stream x DaqStatus:
| 0 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3) | Stream Pause | Debug flag |
bit 0: Raw diagnostic stream control |
Pausepause (Waveform engine bufferDone signal. When an AXI frame is completely written to DRAM, this bit is set) |
1 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3) | Stream Ready | Debug flag: |
bit 1: Raw diagnostic stream control Ready |
bit 2: (Waveform engine FIFO output stream ready signal) |
2 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3) | Stream Overflow | Debug flag: Raw diagnostic stream control Overflow |
bit 3(set to 0 in waveform engine) |
3 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3) | Stream Error | Debug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped) |
bit : Incoming data lane valid bit 5: DAQ Enabled
| ${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3) | Data source ready | Debug signal: The data source is ready. If not, DaqMux sets error signal to 1 |
5 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3) | Stream Enable | Debug signal: Output stream enabled |
31:6 | ${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3) | Frame Count | Number of 4096 word frames sent |
024-0x2F |
|
| Not used |
bit 31-6: Number of packets (4k byte frames) sent0x3F0x3x: Stream x DataFormat:
bit 4-0: DataWidth (Zero inclusive). Selects the sign extension bit.
Note: The sign extension is active if "'1'- Signed" is selected.
The DataWidth should point to the bit number for example: 16-bit data -> DataWidth = 0xF, 32-bit data -> DataWidth = 0x1F
bit 5: '0' - 32-bit, '1'- 16-bit
bit 6: '0' - Unsigned, '1'- Signed
bit 7: Decimation Averaging '0' - Disabled, '1'- Enabled
TBD | TBD4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3) | Sign Bit Position | Indicating sign extension point (all bits after sign bit will be overwritten with sign) |
|
|
| 5 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3) | Data Width | Data width 32-bit or 16-bit - '0' : 32-bits
- '1' : 16-bits
|
|
|
| 6 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3) | Sign enable | Signed/unsigned - '0' : Unsigned
- '1' : Signed
|
|
|
| 7 | ${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3) | Decimation Averaging Enable | Decimation Averaging - '0' : Disable
- '1' : Enable
|
|
|
|
| ${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQ | SW Trigger Pulse | A sequence setting Software Trigger Enable to 1 then 0 |
Legend:
| Not in original requirements document |
| Not exported to EPICS |
*Data Header structure- HeaderWord[0]: dmod(31:0) - Timing pattern information
- HeaderWord[1]: dmod(63:32) - Timing pattern information
- HeaderWord[2]: dmod(95:64) - Timing pattern information
- HeaderWord[3]: dmod(127:96) - Timing pattern information
- HeaderWord[4]: dmod(159:128) - Timing pattern information
- HeaderWord[5]: dmod(191:160) - Timing pattern information
- HeaderWord[6]: timeStamp_i(31:0) – secPastEpoch
- HeaderWord[7]: timeStamp_i(63:32) – nses
- HeaderWord[8]: bsa(127:96) - edefAvgDn
- HeaderWord[9]: bsa(95:64) -edefMinor
- HeaderWord[10]: bsa(63:32) -edefMajor
- HeaderWord[11]: bsa(31:0) -edefInit
- HeaderWord[12]: packetSize_i
- HeaderWord[13]: Firmware specific signals
- [BIT31:BIT27] = "00000"
- [BIT26:BIT26] = Trigger Header: Hardware Trigger – s_trigHw
- [BIT25:BIT25] = Trigger Header: Cascaded Trigger – s_trigCascRe
- [BIT24:BIT24] = Trigger Header: Software Trigger – s_trigSw
- [BIT23:BIT23] = Data format – dec16or32_i
- [BIT22:BIT22] = Enable decimation averaging – averaging_i
- [BIT21:BIT21] = Test mode – test_i
- [BIT20:BIT20] = AMC BAY Index – BAY_INDEX_G
- [BIT19:BIT16] = Channel Index – axiNum_i
- [BIT15:BIT00] = decimation rate divide – rateDiv_i
How to get the DaqMux streams
The DaqMux streams are routed to the DRAM on the application board, and are read using another series of components and exported to the software using the cpswDebugStreamAsynDriverConfigure IOC shell command of the ATCACommon EPICS module, which is out of the scope of this document. This module provides all stream information in format of PVs. The available exported PVs are shown in Table 3. As can be seen, this module exports the streams represented with STR (and no longer with DAQMUX). Usually the software engineer would keep the numbering the same and just changing the string to minimize confusion.
PV name | Description |
---|
${DEVICE}:STR{DAQMUX#}:STREAM_TYPE(0-3) | The data type of the corresponding channel |
${DEVICE}:STR{DAQMUX#}:STREAM_${DATATYPE}(0-3) | The data stream of the corresponding channel on full speed of type ${DATATYPE} ∈ {SHORT, LONG, USHORT, ULONG, DOUBLE, FLOAT} |
${DEVICE}:STR{DAQMUX#}:STREAM_SLOW${DATATYPE}(0-3) | The data stream of the corresponding channel on reduced speed of type ${DATATYPE} ∈ {SHORT, LONG, USHORT, ULONG, DOUBLE, FLOAT} |
Other references