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Task | Description | Status | Date | Owner |
---|---|---|---|---|
AxiLiteCrossbar | Create a xbar for the ASICTOP module | done | Dawood | |
Port ASIC control module | use Register control as copy and paste into the new module | done | Dawood | |
Port trigger module | copy from epix-hr-single-10k | done | Dawood | |
Simulate | Simulate both modules | done | Dawood | |
axilite address space | Define address space for the ASIC top | started | Dawood | |
axiStreamRepeaters | Repeaters for the timing information (x5) | Done |
| Dawood |
axiStreamBatcher | Creates the data package with image and timing info (x5) | Done |
| Dawood |
DigitalAsicStreamV2 | Port to 2m and increase number of ASICs to 4 | Done |
| Dawood |
Synthesis | Make sure design synthesizes completed, update constraints if needed. | Done |
| Dawood |
Software | Complete companion device/register definition, if missing. | Done |
| Dawood |
ASIC Model | Port from simulation test bench an ASIC model to a new HDL entity that will mimic the ASIC data path. Needs a data length counter to send one frame per SRO. Map all IO to the ASIC even though some will not be used for this simulation. | Done |
| Dawood |
DigitalAsicSttreamV3 | Create internal module to de-interleave the images | Dawood | ||
Hardware deployment | Test HW/SW register access | Done |
| Dawood/Dionisio |
Chip scope pro | Integrate chip scope pro | Dionisio | ||
Voltage source test | enable sources and check test points/capacitors for all channels |
| Dawood | |
Slow ADC test | Test current, temperature and humidity | Done | Julian | |
Fast ADC test | Done | Julian | ||
Add serial number and test | Started | Julian | ||
DAC test | apply DAC value and check test points | Done | Dawood | |
SI5345 Jitter cleaner | Generate file and have software write it to jitter cleaner | Dawood | ||
Reproduce timing LCLS-II | Port timing related modifications from HrM , and test timing with KCU1500 | Done | Julian | |
data descrambling in firmware | Dawood |
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