Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Overview

Acronyms

TermDescription

AC

Alternate Current

ATCA

Advanced Telecommunications Computing Architecture

CPU

Central Processing Unit

EPICS

Experimental Physics and Industrial Control System

FPGA

Field Programmable Gate Array

IOC

Input Output Controller

LCLS

Linac Coherent Light Source

NC

Normal-Conducting

RF

Radio Frequency

SC

Super-Conducting

SHM

Shelf Manager

VMTG

VME-based Master Trigger Generator

Linac Locking System-Level Description

...

The 2856MHz from Sector-10 is locked to the 2856MHz from Sector-2, but that doesn't mean that necessarily hold true for their respective 476MHz signals have a known relationship.  To fix thisprovide the triggers we want, we need to align the fiducials.  We need NC and SC timing to align at 71kHz so they can coordinate with the beam generation.  Two options: either design the VME-based Master Trigger Generator (VMTG) which drives the Fiducial Generator at 360Hz to trigger at 71kHz or slide the RF buckets until they align.  The LCLS VMTG samples the AC power line at 71.4kHz the 71kHz subharmonic of its RF input and each 360Hz fiducial is coincident with the 7171kHz. 4kHz subharmonic.  A TPR card processes both timing systems simultaneously and it measures the relative delay between the NC and SC 71.4kHz 71kHz subharmonic.


(Diagram by Matt Weaver)


The idea is to trigger the SC timing system to follow the NC timing system.  The Timing Pattern Generator (TPG) card has 3 TTL inputs for external triggers.  The firmware has the capability to interpret those TTL signals for 1Hz, 60Hz or 360Hz or can also sample the power line to generate independent fiducials. 

...

See firmware release details below.

RepositoryURLVersion
slaclab / EvrLockhttps://github.com/slaclab/evr-card-g2/releases/tag/v2.2.0v2.2.0

References