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1. Login to the supervisory CPU, go to the timing application tool, and source the environment:

   Code Block
   # In Prod, $ ssh mcclogin $ ssh softegr@lcls-srv01 [softegr@lcls-srv01 ~]$ ssh laci@<CPU_NODENAME> [laci@<CPU_NODENAME>]$ cd /usr/local/lcls/package/timing/tpg/R1.4.0/buildroot-2019.08-x86_64/bin # In Dev, $ ssh lcls-dev3 [lcls-dev3 ~]$ ssh laci@<CPU_NODENAME> [laci@<CPU_NODENAME>]$ cd /afs/slac/g/lcls/package/timing/tpg/R1.4.0/buildroot-2019.08-x86_64/bin

2. Configure the timing crossbar in the MPS Link Node carrier (slot 2) to receive the timing signal from the RTM input, and distribute it via the backplane (Here change <SLOT2_IP> by the IP address of the carrier in slot 2)

   Code Block
   [laci@<CPU_NODENAME>]$ ./hps_peek -h Usage: ./hps_peek [options] Options: -a <ip address, dotted notation> -y <yaml file>[,<path to timing>] -d Dump raw timing stream -D Dump framed timing -s Dump stats -S <secs> Dump stats over seconds -t <value> Set timingMode/clkSel -P <value> set polarity -X <output>,<value> set xbar output -x ignore crossbar -r reset FPGA -R reload FPGA

   Code Block
   [laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOT2_IP> -y ../../yamlb/000TopLevel.yaml -t 0 [laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOT2_IP> -y ../../yamlb/000TopLevel.yaml -X 1,0 [laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOT2_IP> -y ../../yamlb/000TopLevel.yaml -X 2,0

   Note
   "-t 0" indicates NC timing mode and "-t 1" specifies SC timing mode.

3. Check that the MPS Link Node carrier (slot 2) is locked to the timing system. In this output:

   1. The carrier is locked to the timing system if the "Link" status says "Up",

   2. you should check that both "OUT[1 (FPGA)]" and "OUT[2 ( BP)]" point to "EVR0". This is the timing source for this carrier.

      Code Block

      [lcls laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOT2_IP> -y ../../yamlb/000TopLevel.yaml -s buildStamp AmcCarrierMpsAnalogLinkNode: Vivado v2018.2, rdsrv221 (x86_64), Built Tue Oct 16 17:03:41 PDT 2018 by ruckman upTime 4316 seconds OUT[0 (EVR0)] = 0 (EVR0) OUT[1 (FPGA)] = 0 (EVR0) OUT[2 ( BP)] = 0 (EVR0) OUT[3 (EVR1)] = 3 (EVR1) RxRecClkFreq: 119.01 TxRefClkFreq: 119.02 Link : Up RxPolarity : 0 SOFcounts : 360 CRCerrors : 0 DECerrors : 0 DSPerrors : 0 [lcls laci@cpu-bsys-sp01]$

4. Now, configure the timing crossbar in the application carriers (starting at slot 3 up to the last slot in the crate) to receive the timing signal from the backplane (Here change <SLOTN_IP> by the IP address of the application carrier you are testing):

   Code Block
   [lcls laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOTN_IP> -y ../../yamlb/000TopLevel.yaml -t 0 [lcls laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOTN_IP> -y ../../yamlb/000TopLevel.yaml -X 1,2

5. Check that the application carrier is locked to the timing system. In this output:

   1. The carrier is locked to the timing system if the "Link" status says "Up",

   2. you should check that "OUT[1 (FPGA)]" points to "2 ( BP)".

   Code Block

   [lcls laci@<CPU_NODENAME>]$ ./hps_peek -a <SLOTN_IP> -y ../../yamlb/000TopLevel.yaml -s buildStamp AmcCarrierKU040LoopbackTester: Vivado v2016.4, rdsrv222 (x86_64), Built Tue Aug 22 23:28:14 PDT 2017 by ruckman upTime 258230 seconds OUT[0 (EVR0)] = 0 (EVR0) OUT[1 (FPGA)] = 2 ( BP) OUT[2 ( BP)] = 0 (EVR0) OUT[3 (EVR1)] = 0 (EVR0) RxRecClkFreq: 119.01 TxRefClkFreq: 119.01 Link : Up RxPolarity : 0 SOFcounts : 361 CRCerrors : 0 DECerrors : 0 DSPerrors : 0

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