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Linac Locking - A System Level Overview

TPR Subsystem Description

The Timing Pattern Receiver (TPR) is an application that replaced the Event Receiver (EVR) for LCLS-II and its purpose is to generate triggers for control, data acquisition and other purposes.  There are two main flavors in which this application is deployed in: (i) as a PCIe board and (ii) as an ATCA board.  The IOC described here is for a PCIe card.  The TPR operates at a faster rate than the EVR (i.e. higher bandwidth), has a more compact frame and also has an LCLS-I timing fiber input, thus allowing it to switch to an LCLS-I operating mode if needed.

IOC Description

Firmware Description

if needed.

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(PCIe TPR - Borrowed from PCIe TPR peer review slide deck, see Reference section below)

The PCIe TPR can provide up to 12 hardware triggers and/or channels.  A channel is a source for a trigger and can be AND-ed or OR-ed with its adjacent channel.  The user is also able to control --besides rate-- polarity, delay and width.  Below, one can find a comprehensive view of the functionality of the TPR that spans firmware, middleware and software.  For more details, please refer to the attached slide deck at the bottom of this page.

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(PCIe TPR Firmware and Software - Borrowed from PCIe TPR peer review slide deck, see Reference section below)

IOC Description

The IOC is used in conjunction with the TPR displays to not only read diagnostics from the firmware, but also set up triggers, assign channels to triggers and timestamp Beam Synchronous Acquisition (BSA) data.

IOC Deployment

In this section, IOC deployment details are provided pertaining to the App hosting the phase locker IOC, as well as the IOC name and the assigned CPUs in both Dev and Production. 

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See firmware release details below.

References 

TPR Documentation

PCIe TPR Peer Review