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Overview

Acronyms

TermDescription

AC

Alternate Current

ATCA

Advanced Telecommunications Computing Architecture

CPU

Central Processing Unit

EPICS

Experimental Physics and Industrial Control System

FPGA

Field Programmable Gate Array

IOC

Input Output Controller

LCLS

Linac Coherent Light Source

NC

Normal-Conducting

RF

Radio Frequency

SC

Super-Conducting

SHM

Shelf Manager

VMTG

VME-based Master Trigger Generator

Linac Locking System-Level Description

A high-level description of the linac locking system is captured in the page linked below:

Linac Locking - A System Level Overview

IOC Description

Firmware Description

A System Level Overview

IOC & Firmware Description

The main objective of this project is to provide triggers to devices on the Super-Conducting (SC) line that are designed to operate on Normal-Conducting (NC) reference frequencies. 

The 2856MHz from Sector-10 is locked to the 2856MHz from Sector-2, but that doesn't necessarily hold true for their respective 476MHz signals.  To provide the triggers we want, we need to align the fiducials.  We need NC and SC timing to align at 71kHz so they can coordinate with the beam generation.  Two options: either design the VME-based Master Trigger Generator (VMTG) which drives the Fiducial Generator at 360Hz to trigger at 71kHz or slide the RF buckets until they align.  The LCLS VMTG samples the AC power line at the 71kHz subharmonic of its RF input and each 360Hz fiducial is coincident with 71kHz.  A TPR card processes both timing systems simultaneously and it measures the relative delay between the NC and SC 71kHz subharmonic.


Image Added

(Diagram by Matt Weaver)


The idea is to trigger the SC timing system to follow the NC timing system.  The Timing Pattern Generator (TPG) card has 3 TTL inputs for external triggers.  The firmware has the capability to interpret those TTL signals for 1Hz, 60Hz or 360Hz or can also sample the power line to generate independent fiducials. 

IOC IOC Deployment

In this section, we provide IOC deployment details such as the App hosting the Trigger Alignment IOC, as well as the IOC name and the assigned CPU in both Dev and Production. 

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Code Block
languagebash
# ===========================================
#               AUTOSAVE
# ===========================================
# Autosave start
< $(TOP)/iocBoot/common/autosave_start.cmd

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EPICS Records

A complete list of the Trigger Alignment IOC Process Variables (PVs) --along with their revision dates, following feedback from the naming team-- can be found in the page linked below.

Linac Locking - Trigger Alignment IOC (PVs [sioc-sys0-ms12) PVs]

Displays

There are no displays for this IOC.

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See firmware release details below.

RepositoryURLVersion
slaclab / EvrLockhttps://github.com/slaclab/evr-card-g2/releases/tag/v2.2.0v2.2.0

References