Page History

• SUGOI = SLAC Ultimate Gateway Operational Interface
• 凄い (or すごい or Sugoi) is a word that's typically used when you're left awestruck out of excitement or feel overwhelmed

Requirements

Requirements

...

• Targeted for ASIC register communication and timing/trigger synchronization
• point-to-point or daisy chain communication
  • Support up to 15 devices in a daisy chain
• Serial Encoding: 8B10B (
  • DC balanced
  )
  • Targeting FPGA/ASIC communication to ASIC over fiber optic or long copper cables
• Serial Rate: Same as reference clock sent to ASIC
• Supports fixed latency communication
• Register access:

  Control Code

  The protocol defines several K-Codes to indicate data framing, flow-control, opcodes, and other metadata. For all K-Codes, the most significant 8 bits of the 64-bit word indicate which code it is. This is known as the Block Type Field (BTF). The next byte after BTF is a 8-bit checksum of entire 64-word (including BTF). The lower 48 bits are then specified differently depending on the K-Code. 
  

  • • Only supports 32-bit aligned addresses and 32-bit word single (non-burst) transactions

  Control Codes
  

  The IDLE code is sent when no data frame and no trigger code is being sent.   The GR is used to send a "global reset" to all the ASIC digital logic. Both IDLE and GR are "comma" codes such that the RX alignment gearbox can align to either of these codes (e.g. power up and start up the ASIC with only setting GR codes for a long period of time).

  Trigger codes can be sent at any time, independent of the state of the data transport.  There are 8 trigger codes that are mapped to a 8-bit trigger operation code bus. When the trigger code is detected in the ASIC, a single cycle strobe will be generate on a bit of this 8-bit trigger bus.
  

  The SOF/EOF codes are used for data framing. After the SOF, the data payload is sent (non-control codes).  After the last data payload byte, the EOF code is sent.  During the data payload transport, any non-SOF or non-EOF control code is allow to be interleaved into the bit stream such that fixed trigger latency on the 8-bit trigger bus can be achieved.
  

  IDLEK28.5

  IDLE	K28.5 (Comma)

  SOF (Start of Frame)	K28.

  1

  0

  EOF (End of Frame)

  K28

  K30.7
  Trigger Code[BIT=0]	K28.2
  Trigger Code[BIT=1]	K28.3
  Trigger Code[BIT=2]	K28.4
  Trigger Code[BIT=3]	K28.6
  Trigger Code[BIT=4]

  K23

  K28.7 (Comma)

  Trigger Code[BIT=5]

  K27

  K23.7

  Trigger Code[BIT=6]

  K29

  K27.7
  Trigger Code[BIT=7]	K29.7
  GR (Global Reset)	K28.1 (Comma)

  Data Frame Format for Register Access
  

  The FPGA sends request messages to the ASIC in the serial protocol data payload tranport (in-between SOF and EOF). The ASIC processes the message and responds back to the FPGA.  Only 1 message is in flight at any time to remove the requirement of back pressuring the link.   Both the request message and responds message are the same size (11 bytes).
  

  The daisy chaining of multiple ASIC is achieved via the header's device address field.  When the ASIC received the header and the device field is 0x1, then the ASIC will process the register request message else pass it through.  For each daisy chain stage and when device address is non-zero, the TX device address field is decremented by 1 from the RX device address.  Example: You have two ASICs in the daisy chain.  You would use device address = 0x1 to do register access on the first device and device address = 0x2 to do register access on the seconds device.

  ASIC Inbound (FPGA Outbound) Request Format

  Byte Offset	Name	Description	Note
  0	Header[7:0]	Version number Operation Type Device Address	BIT[2:0] = 0x1 BIT[3]: 0x1 = READ 0x0 = WRITE BIT[7:4] = Device index on daisy chain
  1	RegAddr[31:24]	Register Address	In units of bytes RegAddr[1:0] must be zero for 32-bit address alignment
  2	RegAddr[23:16]
  3	RegAddr[15:8]
  4	RegAddr[7

  ]K30.7

  :0]
  5	WriteData[31:24]	Write Data	Only used for write operations
  6	WriteData[23:16]
  7	WriteData[15:8]
  8	WriteData[7:0]
  9	Footer[7:0]	Responds  Value	footer bitwise OR'd for all daisy chain responds
  10	Checksum[7:0]	Checksum	Calculated from all data payload bytes ByteOffset[9:0] One's complement

  ASIC Outbound (FPGA Inbound) Response Format

  
  

  Byte Offset	Name	Description	Note
  0	Header[7:0]	Version number Operation Type Device Address	Version number = Echoed back Operation Type = Echoed back Device Address: if 0x0 = Echoed back Else decremented by 1 from request's device address
  1	RegAddr[31:24]	Register Address	Echoed back
  2	RegAddr[23:16]
  3	RegAddr[15:8]
  4	RegAddr[7:0]
  5	MemData[31:24]	Memory Data	Returns the read data if read operation Returns the write data if write operation
  6	MemData[23:16]
  7	MemData[15:8]
  8	MemData[7:0]
  9	Footer[7:0]	Responds  Value	Only used for non-posted operations.  non-zero if error BIT[1:0] = Memory Transaction Responds BIT2 = Version Mismatch Error BIT3 = non 32-bit address alignment BIT4 = checksum error BIT[7:5] = 0x0
  10	Checksum[7:0]	Checksum	Calculated from all data payload bytes ByteOffset[9:0] One's complement

  
  

  References

  • "SLAC Ultimate Gateway Operational Interface (SUGOI) Protocol for Fiber Optic ASIC/FPGA Communication": https://ieeexplore.ieee.org/document/10399282