Digital Signal Processors (DSPs) are microprocessors with the following characteristics:
- Real-time digital signal processing capabilities. DSPs typically have to process data in real time, i.e., the correctness of the operation depends heavily on the time when the data processing is completed.
- High throughput. DSPs can sustain processing of high-speed streaming data, such as audio and multimedia data processing.
- Deterministic operation. The execution time of DSP programs can be foreseen accurately, thus guaranteeing a repeatable, desired performance.
- Re-programmability by software. Different system behaviour might be obtained by re-coding the algorithm executed by the DSP instead of by hardware modifications.
In the pixel detector, a A single Master and four Slave DSPs reside on the board and are utilized
for the control and coordination of on- ROD operations, as well as performing high-level tasks such as
data monitoring and module calibration. Once configured, the ROD FPGAs handle the event data-path
to ATLAS Level-2 without further assistance from the DSPs.
ROD reset and the VME interface are handled by an FPGA referred to as the Program Reset Manager
(PRM). At power-up, the PRM activates the host-to-ROD VME interface and resets the Master DSP
(MDSP). Once the MDSP has booted, configuration information is transmitted for the Controller FPGA
as well as the data-path FPGAs as the Formatter, the Event Fragment Builder and the Router. The farm
of Slave DSPs (SDSPs) are loaded with boot code from the host via the MDSP.
The MDSP is a Texas Instruments 6201 integer DSP running at 160 MHz with two internal 64 kB blocks of memory and an additional 32 MB of (slower) external memory. The MDSP has ROD and BOC registers connected to one of its External Memory InterFaces (EMIFs) thereby allowing any ROD or BOC registers to be set from the host via the MDSP. The MDSP runs software to perform system functions while the FPGA performs real-time functions. Module configuration is performed by the MDSP using
its multi-channel buffered serial ports (SP0 and SP1); configuration data is passed to the MDSP from the
host. In calibration mode the MDSP serial ports are also used to send triggers. During normal ATLAS
running the trigger and event description information (Level-1 ID, bunch-count ID and triggertype) is
supplied to the ROD by the TIM. The TIM trigger is detected inside of the Controller and expanded into
the trigger codes required by the Pixel and SCT modules. The trigger code is then sent out via a 48-wide
mask gate and propagated on to the modules.
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