Why so many bits?
- Axi stream demux (from Ben): lower 0x0000 configures a route-mask and a destination here: https://github.com/slaclab/axi-pcie-core/blob/main/python/axipcie/_AxiGpuAsyncCore.py#L163-L178. upper 0xffff0000. One stream in, two streams out (cpu and gpu). Don't overthink it: just two values (otherwise get into the swamp of the general demux written by Ben that is being reused here)
How do we support multiple GPUs?
How do we support multiple pgp cards per GPU?
Would like power-on default to be to vector the data to the CPU
- Mudit/Ryan say that software initialization has to be done already (e.g. setting up clocks) so not a big deal to do this in software
FYI for TID: Aiming to have the same software work for multiple detectors: e.g. TDet, epixM, epixUHR. "GpuDetector" is analog of "PgpDetector".
Aiming to have the same firmware for GPU/CPU e.g. for TDet.
- Mudit confirms that we will be able to use same firmware for both CPU/GPU deployments
- Should be true for other detectors as well, like epixUHR
Question for Mudit: most TDet registers are in the 0x00a00000 space, but a few (e.g. the switch between cpu/gpu directions) are in the 0x00d00000 space. What's the difference between the two spaces and should the "switch" be moved to 0x00a? (along with everything else, so nothing would be in 0x00d)
- 0xa00000 space has the axi-lite registers for TDetsemi module, following Matt's original code
- 0xd00000 space has the axi-lite registers for the dmux/asyncgpu modules

Image Added

Oct. 28, 2024

Stefano has pyFAI results to compare with his standalone method
Gabriel will perhaps start working on calibration in the GPU
Valerio is working on other projects. regarding move to spack:
- first get psana2 working in s3df with spack
- then get cpu-based daq working with spack
- then incorporate ric's gpu work into spack
- we will split spack in the daq/mini-psana (old system) and big-psana (s3df)
ric has committed his code to git

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