Jira | ||||||
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Photo | SENSOR HV | HV GND | AGND | P24V0A | DGND | P24V0D | |
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Cable 01 - Board 38-C00-02 | 0.6R | 0.7R | 0.4R | 0.4R | 0.3R | 0.3R |
Measuring on test points on the analog board.
P24V0D | P24V0A | ||
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Analog board | 23.96 V | 24.01 V | |
Digital board | 23.96 V | 24.01 V | |
Power supply current | 170 mA | 0.2 mA |
SysMon | Virtual IO | Photo | |
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Only digital board | |||
Digital and analog board | |||
Digital, analog and carrier board |
OM2223-00027 LEAP transceiver | Before mounting | After mounting | After mounting closeup |
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Before mounting | After mounting |
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Analog board thermal pads | Analog board mounted | Digital board thermal pads | Digital board mounted | Cooling plate for the LEAP transceiver |
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System connected up | Internal FPGA temperature after about 20 min |
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WARNING: pciServer.AxiPcieCore.numDmaLanes = 4 != pciServer.AxiPcieCore.AxiVersion.DMA_SIZE_G = 8
python PgpMonitor.py --numLane 8
PGP example project working | PGP lane 5 status in monitor Connected in firmware to SRP | PGP lane 4 status in monitor Not connected in firmware | PGP working on GT Readout! | GT Readout Board Control module Must be enabled first | Board serial IDs |
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The aim of this test is to verify the data rate that can be achieved with the FPGA GTY transceivers that are connected to the Leap transceiver. An external fiber connection is used to loop back the transmitted data back into the received data of the same channel. A simplified gateware is used for the FPGA that contains the IBERT for UltraScale/UltraScale+ GTY Transceivers and interacts with the Vivado Serial I/O Analyzer. A similar setup was used during the testing of the SparkPix-IO ASIC. The 156.25 MHz clock connected to MGTREFCLK1 on bank 133 is used as the reference clock for the GTs and the IBERT.
Using digital board 38-C00-01. Only channel 0 (GT_RX_0 / GT_TX_0) is tested for now because of lack of fiber loopbacks. The loopback is done after the 24-MTP to 12-LC-duplex using a LC-simplex fiber. The temperature is the Internal FPGA temperature read from the system monitor. A 31-bit PRBS is used and the eye is scanned with the highest possibly resolution after the temperature has stabilized inside the FPGA. A full test should have all 12 GTY channels running over a long time period.
5 Gbit/s | 10 Gbit/s | 15 Gbit/s | 20 Gbit/s | 25 Gbit/s | 25.625 Gbit/s | 25.9375 Gbit/s | 26.25 Gbit/s | 27.5 Gbit/s | 28.125 Gbit/s | |
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Eye diagram Without TX pre/post-cursor | ||||||||||
Eye diagram With TX pre/post-cursor | - | - | - | - | pre=0.81 dB, post=0.82 dB | pre=1.3 dB, post=1.32 dB | pre=1.3 dB, post=1.32 dB | pre=1.87 dB, post=1.91 dB | pre=2.28 dB, post=2.28 dB | pre=3.08 dB, post=3.14 dB |
Temperature | 39°C | 40°C | 42°C | 44°C | 49°C | 49°C | 49°C | 48°C | 48°C | 49°C |
P24V0D power | 15.9 W | 16.6 W | 18.3 W | 19.3 W | 21.6 W | 21.7 W | 21.8 W | 21.3 W | 21.4 W | 21.5 W |
Bitfile | ||||||||||
Debug file |
Note: The IBERT module only works up until 28.2 Gbit/s.