Jira | ||||||
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Photo | SENSOR HV | HV GND | AGND | P24V0A | DGND | P24V0D | |
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Cable 01 - Board 38-C00-02 | 0.6R | 0.7R | 0.4R | 0.4R | 0.3R | 0.3R |
Measuring on test points on the analog board.
P24V0D | P24V0A | ||
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Analog board | 23.96 V | 24.01 V | |
Digital board | 23.96 V | 24.01 V | |
Power supply current | 170 mA | 0.2 mA |
SysMon | Virtual IO | Photo | |
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Only digital board | |||
Digital and analog board | |||
Digital, analog and carrier board |
OM2223-00027 LEAP transceiver | Before mounting | After mounting | After mounting closeup |
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Before mounting | After mounting |
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Analog board thermal pads | Analog board mounted | Digital board thermal pads | Digital board mounted | Cooling plate for the LEAP transceiver |
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System connected up | Internal FPGA temperature after about 20 min |
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WARNING: pciServer.AxiPcieCore.numDmaLanes = 4 != pciServer.AxiPcieCore.AxiVersion.DMA_SIZE_G = 8
python PgpMonitor.py --numLane 8
PGP example project working | PGP lane 5 status in monitor Connected in firmware to SRP | PGP lane 4 status in monitor Not connected in firmware | PGP working on GT Readout! | GT Readout Board Control module Must be enabled first | Board serial IDs |
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The aim of this test is to verify the data rate that can be achieved with the FPGA GTY transceivers that are connected to the Leap transceiver. An external fiber connection is used to loop back the transmitted data back into the received data of the same channel. A simplified gateware is used for the FPGA that contains the IBERT for UltraScale/UltraScale+ GTY Transceivers