Page History

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• Both projects have a 371.428571 MHz clock for the GTY
• Both projects have a 156.25 MHz clock with a SI53340 clock buffer with 2x outputs going to the GTY and 1 output to the SI5345B
  • GT Readout has another output to a secondary SI5345B
  • ePixHR250M has test pads for the remaining output
• Both projects have a SI5345B driven from a LMK61E2, a 48 MHz crystal or a clock output from the FPGA. A clock feedback loop is also used
  • GT Readout has:
    • 3x outputs going to the GTY
    • 2x outputs going to the FPGA logic
  • ePixHR250M has:
    • 2x outputs going to the GTY
    • 1x output going to the FPGA logic
    • 1x output going to a SI53340 clock buffer