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Linac Locking System-Level Description

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Linac Locking - A System Level Overview

IOC Description

The main objective of this project is to provide triggers to devices on the Super-Conducting (SC) line that are designed to operate on Normal-Conducting (NC) reference frequencies. 

The 2856MHz from Sector-10 is locked to the 2856MHz from Sector-2, but that doesn't mean that their respective 476MHz signals have a known relationship.  To fix this, we need to align the fiducials.  We need NC and SC timing to align at 71kHz so they can coordinate with the beam generation.  Two options: either design the VME-based Master Trigger Generator which drives the Fiducial Generator at 360Hz to trigger at 71kHz or slide the RF buckets until they align.  The LCLS VMTG samples the AC power line at 71.4kHz subharmonic of its RF input and each 360Hz fiducial is coincident with the 71.4kHz subharmonic.  A TPR card processes both timing systems simultaneously and it measures the relative delay between the NC and SC 71.4kHz subharmonic.

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The idea is to trigger the SC timing system to follow the NC timing system.  The Timing Pattern Generator (TPG) card has 3 TTL inputs for external triggers.  The firmware has the capability to interpret those TTL signals for 1Hz, 60Hz or 360Hz or can also sample the power line to generate independent fiducials. 

Firmware Description

IOC Deployment

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