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For the purpose of Linac Locking, the 476MHz RF signal is the VCO output found in the Resynchronization Chassis.  To generate this, an 11.5MHz VCO input and other RF signals from the Master Oscillator rack (i.e. 162.5MHz and 650MHz) are manipulated in such a way that a 476MHz RF signal is produced.  The SIM crates ensure that the 11.5MHz and 476MHz PLL output signals that are routed back to the Resynchronization Chassis remain locked in phase and frequency with their respective reference signals also taken from the Resynchronization Chassis.  Further down the RF path, the 476MHz signal will be transported to Sector-2 via a (~1Km long) fiber cable and will be designated as the Main Drive Line (MDL) for PCAV, XTCAV and XTCAVmore.

The PLL IOCs expose the SIM PLL FPGA registers to EPICS records, which can then be monitored and/or tuned to ultimately achieve a lock in phase and frequency for the 11.5MHz and 476MHz RF signals.

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