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The SIMs used here are designed to function as Phase Locked Loops (PLLs).  A PLL is an electronic circuit with a voltage controlled oscillator (VCO) that constantly adjusts to match the frequency of an input signal.  PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a noisy communications channel.  The main purpose of a PLL is to synchronize the output signal with a reference signal.  It starts with estimating the phase difference between the input and reference signals.  By constantly adjusting the VCO voltage, a PLL reduces phase errors between output and input frequencies.  When the phase difference between these signals is zero, the system is said to be locked.  Besides synchronizing output and input reference frequencies (i.e. lock the phases), a PLL also helps achieve frequency lock in a circuit.

(Diagram above by Bo Hong)

For the purpose of Linac Locking, the 476MHz RF signal is the VCO output found in the Resynchronization Chassis.  To generate this, an 11.5MHz VCO input and other RF signals from the Master Oscillator rack (i.e. 162.5MHz and 650MHz) are manipulated in such a way that a 476MHz RF signal is produced.  The SIM PLL crates ensure that the 11.5MHz and 476MHz PLL output signals that are routed back to the Resynchronization chassis remain locked in phase and frequency with their respective input reference signals also taken from the Resynchronization chassis. (Diagram above by Bo Hong) Further down the RF path, the 476MHz signal will be transported to Sector-2 via a (~1Km long) fiber cable and will be designated as the Phase Reference Line.

The PLL IOCs expose the SIM PLL FPGA registers to EPICS records, which can then be monitored and/or tuned in order to ultimately achieve a lock in both phase and frequency for the 11.5MHz and 476MHz RF signals.

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