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https://www.thinksrs.com/products/sim.html
The SIMs used here are designed to function as Phase Locked Loops (PLLs). A PLL is an electronic circuit with a voltage controlled oscillator (VCO) that constantly adjusts to match the frequency of an input signal. PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a noisy communications channel. The main purpose of a PLL is to synchronize the output signal with a reference signal. It starts with estimating the phase difference between the input and reference signals. By constantly adjusting the VCO voltage, a PLL reduces phase errors between output and input frequencies. When the phase difference between these signals is zero, the system is said to be locked. Besides synchronizing output and input frequencies (i.e. lock the phases), a PLL also helps achieve frequency lock in a circuit.
For the purpose of Linac Locking, the 476MHz RF signal is the VCO output in the Resynchronization Chassis. To generate this, an 11.5MHz VCO input and other RF signals from the Master Oscillator rack (i.e. 162.5MHz and 650MHz) are manipulated in such a way that a 476MHz signal is produced. The SIM PLL crates ensure that the 11.5MHz and 476MHz output signals that are routed back to the Resynchronization chassis remain locked in phase and frequency with their respective input signals from the Resynchronization chassis. (Diagram below by Bo Hong)
The PLL IOCs expose the SIM PLL FPGA registers to EPICs EPICS records, which can then be monitored and/or configured tuned in order to achieve a lock in both phase and frequency . For the purpose of Linac Locking, the for the 11.5MHz and 476MHz RF signals are used to generate a .
DHCP Configuration
The PLL instrumentation gets assigned IP addresses in order for the IOC to interface with the PLL FPGA registers. See below for the IP addresses assigned to the 11.5MHz and 476MHz PLLs.
| Code Block | ||
|---|---|---|
| ||
[softegr@lcls-srv01 skoufis]$ cat $EPICS_IOCS/cpu-sys0-sp01/iocSpecificRelease/cpuBoot/lcls/cpu-sys0-sp01/dhcpd.conf
...
##########################
# Linac Locking Project #
##########################
# SN = 17
# 11.5MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim17 {
hardware ethernet 08:00:56:00:46:F9;
fixed-address 192.168.1.17;
}
# SN = 18
# 476MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim18 {
hardware ethernet 08:00:56:00:46:FB;
fixed-address 192.168.1.18;
}
|
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