Page History

...

The SIMs used here are designed to function as Phase Locked Loops (PLLs).  A PLL is an electronic circuit with a voltage controlled oscillator (VCO) that constantly adjusts to match the frequency of an input signal.  PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a noisy communications channel.  The main purpose of a PLL is to synchronize the output signal with a reference signal.  It starts with estimating the phase difference between the input and reference signals.  By constantly adjusting the VCO voltage, a PLL reduces phase errors between output and input frequencies.  When the phase difference between these signals is zero, the system is said to be locked.  Besides synchronizing output and input frequencies (i.e. lock the phases), a PLL also helps achieve frequency lock in a circuit.

The PLL IOCs expose FPGA registers to EPICs records, which can then be monitored or configured in order to achieve a lock in phase and frequency.  For the purpose of Linac Locking, the 11.5MHz and 476MHz RF signals are used to generate a 

DHCP Configuration

The PLL instrumentation gets assigned IP addresses in order for the IOC to interface with the PLL FPGA registers.  See below for the IP addresses assigned to the 11.5MHz and 476MHz PLLs.

...