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| Term | Description |
|---|---|
ATCA | Advanced Telecommunications Computing Architecture |
CPU | Central Processing Unit |
EPICS | Experimental Physics and Industrial Control System |
FPGA | Field Programmable Gate Array |
IOC | Input Output Controller |
PLL | Phase Locked Loop |
RF | Radio Frequency |
SHM | Shelf Manager |
VCO | Voltage Controlled Oscillator |
...
IOC Description
DHCP Configuration
The PLL instrumentation gets assigned IP addresses, so that the IOC can interface with the PLL FPGA registers. See below for the IP addresses for the 11.5MHz and 476MHz PLLs.
| Code Block | ||
|---|---|---|
| ||
[softegr@lcls-srv01 skoufis]$ cat $EPICS_IOCS/cpu-sys0-sp01/iocSpecificRelease/cpuBoot/lcls/cpu-sys0-sp01/dhcpd.conf
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##########################
# Linac Locking Project #
##########################
# SN = 17
# 11.5MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim17 {
hardware ethernet 08:00:56:00:46:F9;
fixed-address 192.168.1.17;
}
# SN = 18
# 476MHz PLL control in L2KG02-27
# digital board:
# analog board:
# eFUSE:
host sim18 {
hardware ethernet 08:00:56:00:46:FB;
fixed-address 192.168.1.18;
}
|
IOC Deployment
In this section, we provide IOC deployment details such as the App hosting the PLL IOCs, as well as the IOC names and the assigned CPUs in both Dev and Production.
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Overview
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