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A high-level description of the linac locking system is captured in the page linked below:

Linac Locking - A System Level Overview

IOC Description

The phase locker IOC provides the controls to interface with the phase locker firmware.  The latter takes at its input a VCO-controlled RF signal and an RF-reference signal of the same frequency.  The computed phase error between the two signals is used to estimate a correction voltage that gets applied to the VCO to tune the VCO-generated signal until the two signals are locked together in phase within an acceptable tolerance.  

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In particular for the linac locking system (see diagram above), the RF reference and 2856MHz VCO signals are read in by the ADC and processed in parallel until their phases are extracted. The phase error between the two signals goes through a proportional-integral (PI) controller and low pass filter to get the phase compensation signal, which is then used to adjust the bias voltage applied to the 476MHz VCO. The VCO tuning range at 476MHz is about ±150Hz with respect to the ATCA baseband DAC, which has a ±5 Volts output range. With the loop bandwidth set to 300Hz, a stable phase locking is achieved with a 10 femtosecond differential timing jitter between the VCO signal and the RF reference signal.

IOC Deployment

IOC Repository

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