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changes.mady.by.user Mikhail Dubrovin

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number

of mpi cores

cache-

references

cache-

misses

cyclesinstructionsbranches

branch-

misses

faultspage-faults

L1-dcache-

load-misses

L1-icache-

load-misses

dTLB-

load-misses

iTLB-

load-misses

cmt
14,448,830,55290,374,312222,814,516,280426,700,282,99358,876,394,5842,343,687,188635,183635,1832,158,358,4175,694,0364,282,821890,671
80349,526,509,3835,932,480,81418,768,444,974,03633,983,153,714,2844,684,730,635,234186,649,297,01952,121,42152,121,421171,500,392,922267,672,856339,145,24769,780,394
Ratio (80)/(1)79.465.784.179.679.579.782.082.079.347.079.278.4


2024-02-09 Test of milano216 host with command perf

Use commands with changed list of counters like 

perf stat -e stalled-cycles-backend,stalled-cycles-frontend,ls_l1_d_tlb_miss.all,l1_dtlb_misses,l1_data_cache_fills_all,bp_l1_tlb_miss_l2_tlb_miss.if2m,bp_l1_tlb_miss_l2_tlb_miss,l2_dtlb_misses,l2_itlb_misses  python test-scaling-subproc.py -8


Summary

number of CPU         

stalled-cycles-backendstalled-cycles-frontendls_l1_d_tlb_miss.alll1_dtlb_missesl1_data_cache_fills_all bp_l1_tlb_miss_l2_tlb_miss.if2mbp_l1_tlb_miss_l2_tlb_missl2_dtlb_missesl2_itlb_misses
11438286142309877243322743732845193217946971437017693094833384719026
82105881833342110835917277903017350821218216564874256066124897317193005591821
168796313234  80186918903278927533263371833455134106055331124679766822722110605352
2410413149941  105194908704916732484905660935153938429778433178896219692246915177116
321725105529713858554955671047247666230997687368421681058742393697813532225021599940
56

17892504080

24120493158113677853811354483251206967759521780824267984323449825438164171
64

27304844238

27697522017125899972912580313541414691090462013305095721825860963243825042
120

45388735746

46279264661238206582023765071062640164533283756999341081748830815578261952













References