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Component | Product number | Board | Operation Voltage | Power consumption | N# I/O needed | Needs substitution? |
Quad SPI Configuration Memory | MT25QU01GBBB8E12 | Digital | 1.8 V | Max 50 mA | 4 | No, we can use HR pins |
JTAG | Digital | 1.8/1.5/1.2 V | 4 | No, we can either use HR or go to 1.2V | ||
Analog Monitor (SlowADC) ADC | ADS1217 | Both (key at the analog board, optional at the digital board) | AVDD =3V, DVDD =1.8V | < 1 mA | 7 | Maybe. The datasheet guarantees operation for digital down to 2.7V, in HR250 was put at 1.8. Check if it is fine! |
Analog Monitor MUX (x5) | MAX4734 | may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...) | AVDD =3V | < 1 uA | None | They are controlled by the ADC |
Humidity sensor | HIH_5031_001 | Analog board | 3 V | None | No | |
Thermistor | NTC_NHQM103B375T10 | Carrier | None | No | ||
Oscillators | •371 MHz XLL726371.428571I •156 MHz 536FB156M250DG •48 MHz CX3225SB48000D0FPJC1 | Digital | 2.5 V | Both 1.8 V and 2.5V solutions can be found depending on the voltage we want to use | ||
Clock Fanout | SI53340-B-GM | Digital | 2.5 / 1.8V | Now is 2.5, probably can be switch to 1.8, but since its AC-coupled should not matter. Check if we can remove the 2.5 LDO | ||
Clock Jitter cleaner | SI5345_64QFN | Digital | VDD = 3.3V, DVDD =1.8V | 12 + n. clks | ||
Programmable Oscillator | LMK61E2 | Digital | 3.3 V | Used? | ||
High Speed ADC | AD9249 | Analog | 1.8 V | Max 58mW/channel: 58*12 = 700mW | 38 | No |
ADC_MON_VCM Buffer | AD8607_MSO8 | Analog | 1.8V | |||
Bias DAC (HV Ring) | MAX5443 (DAC) + MAX14611 (Level Shifter) + REF192GS (Voltage reference) | Analog | 3.0 V (VCCA) | 4 | Maybe? Will the sensors have an HV ring? | |
ASIC clk fanout | SI53340-B-GM | Analog | Probably not needed | |||
HS DAC (Vcalib_p) | MAX5719A(DAC)+ MAX14611 (Level Shifter) + OP213 (Buffer) MAX6126A41+(Vref) | Analog | 5V | Why was this chosen? Do we need the 5 V supply? | ||
Level Shifter for Power controllers | MAX3378EETD (x2) MAX3373E_SOT23_8 (x1) | to be defined | 1.8V -> 3.3V | |||
Serial number | DS2411R | Carrier, analog and digital boards | 1.8V | |||
Line Equlizer |
Functionality | IO type | Quantity | switching specification |
---|---|---|---|
ASIC control (GR, ...) | 2.5V SE | Static | |
SUGOI | |||
SACI | |||
DATA | CLM? | 40 + spares? | 10Gbps |
System IO | |||
transceiver | 25Gbps | ||
supporting electronics | |||
enablels for power | |||
Slow ADC (current and voltage monitors, temperature sensors...) | |||
HS ADC | |||
serial number | |||
HS DAC | |||
Lower priority needs (R&D on system) | |||
FPGA to FPGA interconnection | requires GT+specific connector |
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