Confluence will be unusable 23-July-2024 at 06:00 due to a Crowd upgrade.
...
Note |
---|
The tasks and questions below should be looked at as soon as possible since they might be blocking |
Expand | ||
---|---|---|
| ||
|
...
...
Domain | Portion | Final Voltages | LDOs | DC/DC | DC/DC | ||||||
ANALOG | ASIC | G_AS_0 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS. The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W. If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W. The power drawn by the rest of analog voltages should be less than 2W. So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W. Considering the efficiency curves of the DC/DC converters: 34/85%/93% = 43W Total Analog Power | ||
G_AS_1 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | ||||||||
G_AS_2 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||
G_AS_3 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | ||||||||
G_VG_0 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +2.5V | LT3086 (LDO) Max 2.1A | ← +3V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (>90% efficiency for this loads) | ← +6 V | ||||
G_VG_1 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | |||||||||
G_VG_2 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +6 V | ||||||||
G_VG_3 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | |||||||||
G_AS_2V5 2.5V @ <0.5 A | ← +2.5V | ||||||||||
DIGITAL | ASIC | G_DS_0 1.3V @3A | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V For the digital consumption of the ASIC we do not have precise numbers regarding the new CML logic. Let's assume a double consumption w.r.t the LVDS design. 1.3V*6A = 8W LDO losses = 0.5*6A = 3W 11W / 85% / 93% = 14W(ASIC Digital) Regarding the FPGA considering a worst case efficiency of the DC/DC: Worst case scenario, the remaining electronics will draw 1A, multiplied by 5.5V = 5.5W, which before the DCDC will become 5.5W /85 = 7W 42.5W Total Digital Power | ||
G_DS_X 1.3V @???A (CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | ||||||||
G_IO_0 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||
G_IO_X 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | ||||||||
FPGA | VCCINT 0.85V @7.05 A | ← +0.85V | LMZ31530 30 20 A (Around 90% efficiency) | ← +6 V | |||||||
VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX 1.8V @0.7A | ← +1.8V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||||
MGTAVCC +MGTYAVCC 0.9V @3.7A | ← +0.9V | ||||||||||
VCC_1.2V + MGTAVTT + MGTYAVTT 1.2V @5.5A | ← +1.2V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (Between 80 and 90 efficiency) | ← +6 V | ||||||||
DAC/ADC/Misc | VDD_5V +5V @ <1A | ← 5V | LT3086 (LDO) Max 2.1A | ← +5.5V (TBD) | |||||||
VDD_3V3 +3.3V @ <1A | ← +3.3V | LT3086 (LDO) Max 2.1A | |||||||||
VDD_1V8 +1.8V @ <1A | ← +1.8V | LT3086 (LDO) Max 2.1A | |||||||||
85.5W Total Power (Estimation without CML transceivers) |
...
Component | Product number | Quantity | Input Voltage | Output Voltage | Max Current | Comment |
DC/DC Step Down converter | LT8648S | 4 | 3V to 42V | 0.6V to 42V | 15A | |
DC/DC PMIC | TPSM5D1806 | 7 | 4.5V to 15V | 0.5V to 5.5V | Dual 6A / Single 12A | |
DC/DC Buck converter | LMZ31530LMZ31520 | 1 | 3V to 14.5V | 0.6V to 3.6V | 20A | 30A Not in stock, replace with TPSM846C24? Other option is TPS53355 that is the IC used inside of LMZ31530.version (LMZ31530) not in stock |
Low Noise LDO | LT1764 | 8 | 2.7V to 20V | 1.21V to 20V | 3A | Low Output Noise: 40µVRMS (10Hz to 100kHz) |
LDO alternative to LT1764 | LT3083 | 8 | 1.2V to 23V | Adjustable to 0V | 3A | Low Output Noise: 40μVRMS (10Hz to 100kHz) |
Low Noise LDO | LT3086 | 12 | 1.4V to 40V | 0.4V to 32V | 2.1A | Low Output Noise: 40µVRMS (10Hz to 100kHz) |
Negative Linear Regulator | LT3091 | 8 | –1.5V to –36V | 0V to –32V | -1.5A | Low Output Noise: 18µVRMS (10Hz to 100kHz) |
...
Gliffy Diagram | ||||||||
---|---|---|---|---|---|---|---|---|
|
Expand | ||
---|---|---|
| ||
OLD Graph: |
...
Expand | ||
---|---|---|
| ||
For single ended → check the electrical specification |
Component | Product number | Board | Operation Voltage | Power consumption | N# I/O needed | Needs substitution? |
Quad SPI Configuration Memory | MT25QU01GBBB8E12 | Digital | 1.8 V | Max 50 mA | 4 | No, we can use HR pins |
JTAG | Digital | 1.8/1.5/1.2 V | 4 | No, we can either use HR or go to 1.2V | ||
Analog Monitor (SlowADC) ADC | ADS1217 | Both (key at the analog board, optional at the digital board) | AVDD =3V, DVDD =1.8V | < 1 mA | 7 | Maybe. The datasheet guarantees operation for digital down to 2.7V, in HR250 was put at 1.8. Check if it is fine! |
Analog Monitor MUX (x5) | MAX4734 | may be needed depending on the number of channels we decide to monitor (all voltages and currents to the ASIC, humidity,...) | AVDD =3V | < 1 uA | None | They are controlled by the ADC |
Humidity sensor | HIH_5031_001 | Analog board | 3 V | None | No | |
Thermistor | NTC_NHQM103B375T10 | Carrier | None | No | ||
Oscillators | •371 MHz XLL726371.428571I •156 MHz 536FB156M250DG •48 MHz CX3225SB48000D0FPJC1 | Digital | 2.5 V | Both 1.8 V and 2.5V solutions can be found depending on the voltage we want to use | ||
Clock Fanout | SI53340-B-GM | Digital | 2.5 / 1.8V | Now is 2.5, probably can be switch to 1.8, but since its AC-coupled should not matter. Check if we can remove the 2.5 LDO | ||
Clock Jitter cleaner | SI5345_64QFN | Digital | VDD = 3.3V, DVDD =1.8V | 12 + n. clks | ||
Programmable Oscillator | LMK61E2 | Digital | 3.3 V | Used? | ||
High Speed ADC | AD9249 | Analog | 1.8 V | Max 58mW/channel: 58*12 = 700mW | 38 | No |
ADC_MON_VCM Buffer | AD8607_MSO8 | Analog | 1.8V | |||
Bias DAC (HV Ring) | MAX5443 (DAC) + MAX14611 (Level Shifter) + REF192GS (Voltage reference) | Analog | 3.0 V (VCCA) | 4 | Maybe? Will the sensors have an HV ring? | |
ASIC clk fanout | SI53340-B-GM | Analog | Probably not needed | |||
HS DAC (Vcalib_p) | MAX5719A(DAC)+ MAX14611 (Level Shifter) + OP213 (Buffer) MAX6126A41+(Vref) | Analog | 5V | Why was this chosen? Do we need the 5 V supply? | ||
Level Shifter for Power controllers | MAX3378EETD (x2) MAX3373E_SOT23_8 (x1) | to be defined | 1.8V -> 3.3V | |||
Serial number | DS2411R | Carrier, analog and digital boards | 1.8V |
Functionality | IO type | Quantity | switching specification |
---|---|---|---|
ASIC control (GR, ...) | 2.5V SE | Static | |
SUGOI | |||
SACI | |||
DATA | CLM? | 40 + spares? | 10Gbps |
System IO | |||
transceiver | 25Gbps | ||
supporting electronics | |||
enablels for power | |||
Slow ADC (current and voltage monitors, temperature sensors...) | |||
HS ADC | |||
serial number | |||
HS DAC | |||
Lower priority needs (R&D on system) | |||
FPGA to FPGA interconnection | requires GT+specific connector |
...
Expand |
---|
DC/DC
Connectors:
FPGA:
Thermistor, humidity:
AD/DA:
ID:
Optical:
Memory:
Oscillator/clock:
Level-shifters:
|
...