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Table of Contents
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High priority tasks and questions
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The tasks and questions below should be looked at as soon as possible since they might be blocking |
- On which board does the power connector (TFM) go?
- Does the digital board need the analog ground (AGND)? (see grounding)
- Can the DC/DC architecture be simplified? Some ICs not in stock, see DC/DC converters
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ASIC level requirements summary
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Domain | Portion | Final Voltages | LDOs | DC/DC | DC/DC | ||||||
ANALOG | ASIC | G_AS_0 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V The current drawn by the 0.6V current sink should not be counted twice since its sourced by the G_AS. The power drawn by the ASIC analog part is 1.3V*4.4A*4= 23W. If using 1.8V as the LDO input, we are burning also (1.8-1.3)V*4.4A*4 = 9W. The power drawn by the rest of analog voltages should be less than 2W. So the power that the DC/DC converters have to provide is around 23 + 9 + 2 = 34W. Considering the efficiency curves of the DC/DC converters: 34/85%/93% = 43W Total Analog Power | ||
G_AS_1 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | ||||||||
G_AS_2 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||
G_AS_3 1.3V @4.4A | ← +1.3V | LT1764 x2 (LDO) Max 6A (= 3A x2) | ← +1.8V (TBD) | ||||||||
G_VG_0 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +2.5V | LT3086 (LDO) Max 2.1A | ← +3V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (>90% efficiency for this loads) | ← +6 V | ||||
G_VG_1 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | |||||||||
G_VG_2 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | ← +6 V | ||||||||
G_VG_3 0.6V @ -2.75A | ← +0.6V | LT3091 x2 (LDO) Max 3.0A (= 1.5A x2) | |||||||||
G_AS_2V5 2.5V @ <0.5 A | ← +2.5V | ||||||||||
DIGITAL | ASIC | G_DS_0 1.3V @3A | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | LT8648S x2 42V, 15A Synchronous Step-Down Silent Switcher 2 Max Current = 15*2 = 30A (Around 93% efficiency for 24 to 6V at max load) | ← +24 V For the digital consumption of the ASIC we do not have precise numbers regarding the new CML logic. Let's assume a double consumption w.r.t the LVDS design. 1.3V*6A = 8W LDO losses = 0.5*6A = 3W 11W / 85% / 93% = 14W(ASIC Digital) Regarding the FPGA considering a worst case efficiency of the DC/DC: Worst case scenario, the remaining electronics will draw 1A, multiplied by 5.5V = 5.5W, which before the DCDC will become 5.5W /85 = 7W 42.5W Total Digital Power | ||
G_DS_X 1.3V @???A (CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | ||||||||
G_IO_0 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||
G_IO_X 1.3V @???A(CML simulations?) | ← +1.3V | LT3086 x2 (LDO) Max 4.2A (= 2.1A x2) | ← +1.8V (TBD) | ||||||||
FPGA | VCCINT 0.85V @7.05 A | ← +0.85V | LMZ31530 30 A (Around 90% efficiency) | ← +6 V | |||||||
VCCAUX + VCC_1.8V +VCCADC + MGTVCCAUX+ MGTYVCCAUX 1.8V @0.7A | ← +1.8V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (85% efficiency for max load at Vout = 1.8V) | ← +6 V | ||||||||
MGTAVCC +MGTYAVCC 0.9V @3.7A | ← +0.9V | ||||||||||
VCC_1.2V + MGTAVTT + MGTYAVTT 1.2V @5.5A | ← +1.2V | TPSM5D1806 (DC/DC) PMIC 4.5-V to 15-V input Dual 6A output (Between 80 and 90 efficiency) | ← +6 V | ||||||||
DAC/ADC/Misc | VDD_5V +5V @ <1A | ← 5V | LT3086 (LDO) Max 2.1A | ← +5.5V (TBD) | |||||||
VDD_3V3 +3.3V @ <1A | ← +3.3V | LT3086 (LDO) Max 2.1A | |||||||||
VDD_1V8 +1.8V @ <1A | ← +1.8V | LT3086 (LDO) Max 2.1A | |||||||||
85.5W Total Power (Estimation without CML transceivers) | |||||||||||
| Anchor | ||||
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Component | Product number | Quantity | Output Voltage | Max Current | Comment |
| DC/DC Step Down converter | LT8648S | 4 | // | 15 A | |
| DC/DC PMIC | TPSM5D1806 | 7 | 0.5 V to 5.5 V | Dual 6 A / Single 12 A | |
| DC/DC Buck converter | LMZ31530 | 1 | 0.6 V to 3.6 V | 30 A | Not in stock, replace with TPSM846C24? Other option is TPS53355 that is the IC used inside of LMZ31530. |
| Low Noise LDO | LT1764 | 8 | 1.21V to 20V | 3 A | Low Output Noise: 40µVRMS (10Hz to 100kHz) |
| Low Noise LDO | LT3086 | 12 | 0.4V to 32V | 2.1A | Low Output Noise: 40µVRMS (10Hz to 100kHz) |
| Negative Linear Regulator | LT3091 | 8 | –1.5V to –36V | -1.5 A | Low Output Noise: 18µVRMS (10Hz to 100kHz) |
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