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From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps @140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps @1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps @1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps @4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps |
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ASIC Power Requirement | Analog Section | Digital Section | 0.6V Sink | Analog TPS | ||||
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ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | |
Voltage | 1.3 V | 1.3V | 1.3V | 1.3V | ??? Maybe | 0.6 V | 2.5 V | 2.5V |
Required current | 10A (= 2.5 A* 4 ASIC) | 13.4 A (= 3.35A * 4 ASIC) | - With LVDS transceivers ???? | - With LVDS transceivers ???? | ??? (If existing lower or equal than SparkPixS) | -8 A | 0.4 A (=0.1 * 4) | 0.4 A (=0.1 * 4) |
System Requirement | +1.3 V @ +17.5 A (+30% current safety margin) | +1.3 V @ +3 A (+30% current safety margin) [waiting for the CML number] | +0.6 V @ -11 A (+30% current safety margin) | +2.5 V @ +0.5 A (+30% current safety margin) | ||||
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Other notes
- FPGA intercommunication
- Co-design with the data reduction pipeline
- DFX for streaming pre-processing and eventually microAI, reusable building blocks
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- Using Altium Designer
- Based mechanically on the boards from ePixHR250M_2x2_Camera_Documentation
- Carrier board (PC_261_101_24_C00)
- Digital board (PC_261_101_25_C00)
- Power & communication board (PC_261_101_26_C00)
- Changes done to the system architecture compared to the boards in the camera above:
- The digital board with the FPGA will be moved to the bottom of the stack with the optical transceiver
- The analog board is at the top and interfaces between the carrier and the digital board
- Naming:
- NNN-single-carrier
- NNN-single-digital
- NNN-single-analog
Where NNN is the "brand name" of this system
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Components marked with DC/DC
Connectors:
FPGA:
Thermistor, humidity:
AD/DA:
ID:
Optical:
Memory:
Oscillator/clock:
Level-shifters:
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are available from the Altium Manufacturer Part Search catalog with symbol and footprintDigital board
The digital board contains the FPGA, supporting ICs and the Amphenol optical transceiver module. The DC/DC on this board are the ones related to the components located here.
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Analog board
The analog board contains all the DC/DC converters that are needed to support the different power rails of the ASICs (see above). The data and control signals between the ASICs and the FPGA are routed through this board between then two high-density connectors.
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Carrier board
The carrier board contains the specific ASICs and any passive components that are needed.
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Overview
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