Page History
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Parameter (estimated) | Small Camera ePixHR/UHR – 140k 2 x 2 ASIC | Super tile ePixHR/UHR – 1.1M 6 x 6 ASIC | Super tile ePixHR/UHR – 1M 6 x 5 ASIC | Small Camera SparkPix S – 500k 2 x 2 ASIC | Quad Camera SparkPix S – 2M 4 x 4 ASIC |
Pixels | 129,024 px (168 *192*4) | 1,161,216 px (168 *192*36) | 967,680 (168 *192*30) | 540,672 px (352*384*4) | 2,162,688 px (352*384*16) |
Rate | 35kHz / 100kHz | 35kHz / 100kHz | 35kHz / 100kHz | 1MHz | 1MHz |
Focal Plane Area | 4cm x 4cm | 12cm x 12cm | 12cm x 10cm | 4cm x 4cm | 8cm x 8cm |
Front side footprint (window) | 5cm x 5cm | 14cm x 14cm | 14cm x 12cm | 5cm x 5cm | 10cm x 10cm |
Power (only ASIC) | 0.016 kW/??? | 0.144 kW/??? | 0.130 kW/??? | 0.021kW | 0.084 kW |
Weight | 1.5kg | 10kg | 9Kg | 1.5kg | 6kg |
Data volume | 56 Gbps/ 160 Gbps | 504 Gbps/ 1440 Gbps | 420 Gbps/ 1190 Gbps | 160 Gbps | 640 Gbps |
ASIC Power Requirements
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ASIC Power
Requirement
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Analog Section
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Digital Section
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0.6V Sink
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Analog TPS
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ePixUHR 140k
2x2 Detector
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SparkPix-S 500k 2x2 Detector
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ePixUHR 140k 2x2 Detector
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SparkPix-S 500k 2x2 Detector
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ePixUHR 140k 2x2 Detector
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SparkPix-S 500k 2x2 Detector
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ePixUHR 140k 2x2 Detector
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SparkPix-S 500k 2x2 Detector
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Voltage
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1.3 V
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1.3V
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1.3V
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1.3V
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??? Maybe
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0.6 V
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2.5 V
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2.5V
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Required current
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10A
(= 2.5 A* 4 ASIC)
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13.4 A
(= 3.35A * 4 ASIC)
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- With LVDS transceivers
1.2 A (= 4* 0.3 A)
-With CML transceivers
????
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- With LVDS transceivers
2.0 A (= 4* 0.5 A)
-With CML transceivers
????
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??? (If existing lower or equal than SparkPixS)
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-8 A
(= -2A * 4 ASIC)
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0.4 A
(=0.1 * 4)
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0.4 A
(=0.1 * 4)
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System Requirement
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+1.3 V @ +17.5 A
(+30% current safety margin)
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+1.3 V @ +3 A
(+30% current safety margin)
[waiting for the CML number]
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+0.6 V @ -11 A
(+30% current safety margin)
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+2.5 V @ +0.5 A
(+30% current safety margin)
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| title | ePixUHR Throughput Calculations |
|---|
From ASIC to FPGA
168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame
@35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps
@100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps
From FPGA to PC
168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame
@32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps
@140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps
@1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps
@1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps
@4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps
| Expand | ||
|---|---|---|
| ||
From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps @140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps @1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps @1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps @4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps |
ASIC Power Requirements
ASIC Power | Analog Section | Digital Section | 0.6V Sink | Analog TPS | ||||
ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | ePixUHR 140k 2x2 Detector | SparkPix-S 500k 2x2 Detector | |
Voltage | 1.3 V | 1.3V | 1.3V | 1.3V | ??? Maybe | 0.6 V | 2.5 V | 2.5V |
Required current | 10A (= 2.5 A* 4 ASIC) | 13.4 A (= 3.35A * 4 ASIC) | - With LVDS transceivers ???? | - With LVDS transceivers ???? | ??? (If existing lower or equal than SparkPixS) | -8 A | 0.4 A (=0.1 * 4) | 0.4 A (=0.1 * 4) |
System Requirement | +1.3 V @ +17.5 A (+30% current safety margin) | +1.3 V @ +3 A (+30% current safety margin) [waiting for the CML number] | +0.6 V @ -11 A (+30% current safety margin) | +2.5 V @ +0.5 A (+30% current safety margin) | ||||
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FPGA Selection
ePixUHR 140k 2x2 Detector Specs | ePixUHR 1.1M 6x6 Detector Specs | ePixUHR 1M 6x5 Detector Specs | SparkPix-S 500k 2x2 Detector Specs | SparkPix-S 2M 4x4 Detector Specs | KU15P (-A1156) Kintex Ultrascale+ FPGA USED IN ePixHR250M | KU15P (-E1517) Kintex Ultrascale+ | KU15P (-A1760) Kintex Ultrascale+ | XCVU160 (-C2104) Virtex Ultrascale | XCVU190 (-A2577) Virtex Ultrascale | VU13P (-A2577) Virtex Ultrascale+ | |
General IO (HD, HP) | 48 HD, 486 HP | 96 HD, 416 HP | 96 HD, 416 HP | 52 HD, 364 HP | 0 HD, 448 HP | 0 HD, 448 HP | |||||
High Speed GTs (GTH/GTY) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceiver) Total: 48 High Speed GTs | - ASIC data: 288 = 8 lanes * 36 ASIC - Spare outputs : 0 - PGP communication: 72 = 12* 1.44 Tbps/ 275Gbps (6 Amphenol Transceivers) Total: 360 High Speed GTs | - ASIC data: 240 = 8 lanes * 30 ASIC - Spare outputs : 0 - PGP communication: 72 = 12 lanes * 1.19 Tbps/ 275Gbps (6 Amphenol Transceivers) Suggested 3 transceivers 1.4x compression in the detector Total: 312 High Speed GTs (If considering 5x2 Modules, 104 GTs each) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceivers) Total: 48 High Speed GTs | - ASIC data: 128 = 8 lanes * 16 ASIC - Spare outputs : 0 - PGP communication: 24* = 12* 495 Gbps/ 275Gbps (2 Amphenol Transceivers) Total: 152 High Speed GTs | 28 | 56 (32 GTH/24 GTY) | 76 (44 GTH/32 GTY) | 104 (52 GTH/52 GTY) | 120 (60 GTH/60 GTY) | 128 (0 GTH/128 GTY) |
Total Block RAM | 34.6 Mb | 34.6 Mb | 34.6 Mb | 115.2 Mb | 132.9 Mb | 94.5 Mb | |||||
UltraRam, HBM | 36 Mb, None | 36 Mb, None | 36 Mb, None | None, None | None, None | 360 Mb, None | |||||
Transceiver Speed (GTH, GTY) | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | GTH 16.3 Gb/s GTY 16.3 Gb/s Transceivers | GTH 16.3 Gb/s GTY 32.75 Gb/s Transceivers | GTH 16.3 Gb/s GTY 32.75 Gb/s Transceivers | GTH 16.3 Gb/s GTY 30.5 Gb/s Transceivers | GTH 16.3 Gb/s GTY 30.5 Gb/s Transceivers | GTY 32.75 Gb/s Transceivers |
Size | The PCB width is (preferably) 65 mm (2.56’’) | 35 x 35 mm | 40 x 40 mm | 42.5 x 42.5 mm | 47.5x47.5 mm | 52.5 x 52.5 mm | 52.5 x 52.5 mm | ||||
Cost | 5-9 k$ | 6-10k$ | 6-10 k$ | 40 k$ | 50-70 k$ | 60-110 k$ | |||||
Comments | The number of GTs in this FPGA does not fit any of the cameras we are targetting | This is fine for the 2x2 Systems. For the larger systems we need more than 3 FPGAs | This is fine for the 2x2 Systems. This is fine for the SparkPix-S 4x4 | This is fine for the 2x2 Systems. | This is fine for the 2x2 Systems (assuming we can fit the real estate). | This is fine for the 2x2 Systems.(assuming we can fit the real estate) |
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