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Target Cameras

                

Parameter

(estimated)

Small Camera 

ePixHR/UHR – 140k

2 x 2 ASIC

Super tile

ePixHR/UHR – 1M

6 x 6 ASIC

Super tile

ePixHR/UHR – 1M

6 x 5 ASIC

Small Camera 

SparkPix S – 500k

2 x 2 ASIC

Quad Camera 

SparkPix S – 2M

4 x 4 ASIC

Pixels

129,024 px

(168 *192*4)

1,161,216 px

(168 *192*36)

967,680

(168 *192*30)

540,672 px

(352*384*4)

2,162,688 px

(352*384*16)

Rate

35kHz / 100kHz

35kHz / 100kHz

35kHz / 100kHz

1MHz

1MHz

Focal Plane Area

4cm x 4cm

12cm x 12cm

12cm x 10cm

4cm x 4cm

8cm x 8cm

Front side footprint (window)

5cm x 5cm

14cm x 14cm

14cm x 12cm

5cm x 5cm

10cm x 10cm

Power (ASIC)

0.06kW / 0.15kW

0.35kW / 0.95kW

0.31kW/0.83KW

0.5kW

2.0kW

Weight

1.5kg

10kg

9Kg

1.5kg

6kg

Data volume 

56 Gbps/ 160 Gbps

504 Gbps/ 1440 Gbps

420 Gbps/ 1190 Gbps

160 Gbps

640 Gbps



Expand
titlePower Breakdown









Expand
titleePixUHR Throughput Calculations

From ASIC to FPGA

          168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame

@35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps

@100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps


From FPGA to PC

168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame

@32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps

@140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps

@1M - 30 ASIC (35kHz/100kHz): 420 Gbps / 1.19 Tbps

@1.1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps

@4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps

@16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps


FPGA Selection


ePixUHR 140k

2x2 Detector

Specs

ePixUHR 1.1M

6x6 Detector

Specs

ePixUHR 1M

6x5 Detector

Specs

SparkPix-S 500k

2x2 Detector

Specs

SparkPix-S 2M

4x4 Detector

Specs

KU15P (-A1156)

Kintex Ultrascale+

FPGA USED IN

Hr-M

ePixHR250M

KU15P (-E1517)

Kintex Ultrascale+

KU15P (-

E1517

A1760)

Kintex Ultrascale+

XCVU160 (-C2104)

Virtex Ultrascale

XCVU190 (-A2577)

Virtex Ultrascale

KU15P (-A1760)

Kintex Ultrascale+

VU13P (-A2577)

Virtex Ultrascale+

General IO (HD, HP)






48 HD, 486 HP

96 HD, 416 HP

96 HD, 416 HP

52 HD, 364 HP

0 HD, 448

HP96 HD, 416

HP

0 HD, 448 HP

High Speed GTs (GTH/GTY)

- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbps/ 275Gbps

(1 Amphenol Transceiver)

Total:

48 High Speed GTs

- ASIC data:

288 = 8 lanes * 36 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12* 1.44 Tbps/ 275Gbps

(6 Amphenol Transceivers)

Total:

360 High Speed GTs

- ASIC data:

240 = 8 lanes * 30 ASIC

- Spare outputs :

0

- PGP communication:

72 = 12 lanes * 1.19 Tbps/ 275Gbps

(6 Amphenol Transceivers)

Suggested 3 transceivers 1.4x compression in the detector

Total:

312 High Speed GTs

(If considering 5x2 Modules, 104 GTs each)


- ASIC data:

32 = 8 lanes * 4 ASIC

- Spare outputs :

4

- PGP communication:

12 = 12* 160 Gbps/ 275Gbps

(1 Amphenol Transceivers)

Total:

48 High Speed GTs

- ASIC data:

128 = 8 lanes * 16 ASIC

- Spare outputs :

0

- PGP communication:

24* = 12* 495 Gbps/ 275Gbps

(2 Amphenol Transceivers)

Total:

152 High Speed GTs

28
(20 GTH/8 GTY)

56

(32 GTH/24 GTY)

104

76

(

52

44 GTH/

52

32 GTY)

120

104

(

60

52 GTH/

60

52 GTY)

76

120

(

44

60 GTH/

32

60 GTY)

128

(0 GTH/128 GTY)

Total Block RAM






34.6 Mb

34.6 Mb

34.6 Mb

115.2 Mb

132.9

Mb34.6

Mb

94.5 Mb

UltraRam, HBM






36 Mb, None

36 Mb, None

None

36 Mb, None

None, None

36 Mb

None, None

360 Mb, None

Transceiver Speed

 (GTH, GTY)

> 10 Gbps

> 10 Gbps

> 10 Gbps

> 10 Gbps

> 10 Gbps

GTH 16.

3Gb

3 Gb/s

GTY

32

16.

75Gb

3 Gb/s

Transceivers

GTH 16.

3Gb

3 Gb/s

GTY 32.

75Gb

75 Gb/s

Transceivers

GTH 16.

3Gb

3 Gb/s

GTY

30

32.

5Gb

75 Gb/s

Transceivers

GTH 16.

3Gb

3 Gb/s

GTY 30.

5Gb

5 Gb/s

Transceivers

GTH 16.

3Gb

3 Gb/s

GTY

32

30.

75Gb

5 Gb/s

Transceivers

GTY 32.

75Gb

75 Gb/s

Transceivers

Size

The PCB width is (preferably) 65 mm (2.56’’)





35 x 35 mm

40 x 40 mm

47

42.

5x47

5 x 42.5 mm

52

47.

5 x 52

5x47.5 mm

42

52.5 x

42

52.5 mm

52.5 x 52.5 mm

Cost

 k$






5-9 k$

 6-10k$

6-10 k$

 6-10k$

40 k$

50-70 k$

6-10 k$

60-110 k$

Comments






The number of GTs in this FPGA does not fit any of the cameras we are targetting

This is fine for the 2x2 Systems.

For the larger systems we need more than 3 FPGAs

This is fine for the 2x2 Systems.

This is fine for the

2x2 Systems (assuming we can fit the real estate).

SparkPix-S 4x4

This is fine for the 2x2 Systems.

This is fine for the

SparkPix-S 4x4

2x2 Systems (assuming we can fit the real estate).

This is fine for the 2x2 Systems.(assuming we can fit the real estate)

*Done considering 1% Occupancy instead of maxing out the transceivers

...



UHR 2x2SparkPix S 2x2SparkPix S 4x4UHR 5x6UHR 6x6

                              Requirements

Characteristics 

48 GTs48 GTs152 GTs312 GTs360 GTs

KU15P (-A1156) Kintex U+

28 GTs    / 352 mm2       / 10k$❌❌❌❌❌
KU15P (-E1517) Kintex U+56 GTs    / 402 mm2      / 10k$✅✅❌❌❌
KU15P (-A1760) Kintex U+76 GTs    / 42.52 mm2  / 10k$✅✅✅ (2 FPGA)❌❌
XCVU160 (-C2104) Virtex U104 GTs / 47.52 mm2  / 40k$✅✅✅ (2 FPGA)✅ (1 FPGA/module)❌
XCVU190 (-A2577) Virtex U120 GTs / 47.52 mm2  / 70k$✅✅✅(2 FPGA)✅ (1 FPGA/module)✅ (1 FPGA/module)
VU13P (-A2577) Virtex U+128 GTs / 52.52 mm2 / 110k$✅✅✅(2 FPGA)✅ (1 FPGA/module)✅ (1 FPGA/module)

...