Confluence will be unusable 23-July-2024 at 06:00 due to a Crowd upgrade.
Requirement | ePixUHR | SparkPix-S | SparkPix-ED |
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frame rate | 100kfps | 1Mfps | 1Mfps |
Power supplies | 2.5V Analog 1.3V (AS/DS/IO) | 2.5V Analog 1.3V (AS/DS/IO) 0.6V (Current sink!) | 1.2V (AS/DS/IO) |
Power for each supply | ePixUHR - 35 kHz | SparkPix-S: supply/ground and power consumption | t.b.d. |
Number of GT IOs per ASIC | 8 (outputs) | 8 (outputs) 1 clock in | t.b.d |
Expected I/O speed | 5.25 Gb/s | 5.25 Gb/s | 10 Gb/s |
Total data bandwidth | 42 Gbit/s | 38 Gbit/s | |
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From ASIC to FPGA 168 * 192 * 12 bit * 14/12 (encoding) = 451,584 bit/frame @35 kHz framerate: 451,584 bit/frame * 35 kHz = 15.8 Gbps @100 kHz framerate: 451,584 bit/frame * 100 kHz = 45.2 Gbps From FPGA to PC 168 * 192 * 12 bit * 66/64 (PGP encoding) = 399,168 bit/frame @32k - 1 ASIC (35kHz/100kHz): 14 Gbps / 40 Gbps @140k - 4 ASIC (35kHz/100kHz): 56 Gbps / 160 Gbps @1M - 36 ASIC (35kHz/100kHz): 504 Gbps / 1.44 Tbps @4M - 144 ASIC (35kHz/100kHz): 2 Tbps/ 5.76 Tbps @16M - 576 ASIC (35kHz/100kHz): 8.1 Tbps / 23 Tbps |
ePixUHR 140k 2x2 Detector Specs | ePixUHR 1M 6x6 Detector Specs | SparkPix-S 500k 2x2 Detector Specs | SparkPix-S 2M 4x4 Detector Specs | XCVU160 (-C2104) Virtex Ultrascale | XCVU190 (-A2577) Virtex Ultrascale | KU15P (-A1760) Kintex Ultrascale+ | VU13P (-A2577) Virtex Ultrascale+ | |
General IO (HD, HP) | 52 HD, 364 HP | 0 HD, 448 HP | 96 HD, 416 HP | 0 HD, 448 HP | ||||
High Speed IO (GTH/GTY) | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceiver) Total: 48 High Speed IOs | - ASIC data: 288 = 8 lanes * 36 ASIC - Spare outputs : 0 - PGP communication: 72 = 12* 1.44 Tbps/ 275Gbps (6 Amphenol Transceivers) Total: 360 High Speed IOs | - ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (3 Amphenol Transceivers) Total: 48 High Speed IOs | - ASIC data: 128 = 8 lanes * 16 ASIC - Spare outputs : 0 - PGP communication: 24* = 12* 495 Gbps/ 275Gbps (2 Amphenol Transceivers) Total: 152 High Speed IOs | 104 (52 GTH/52 GTY) | 120 (60 GTH/60 GTY) | 76 (44 GTH/32 GTY) | 128 (0 GTH/128 GTY) |
Total Block RAM | 115.2 Mb | 132.9 Mb | 34.6 Mb | 94.5 Mb | ||||
UltraRam, HBM | None, None | None, None | 36 Mb, None | 360 Mb, None | ||||
Transceiver Speed (GTH, GTY) | > 10 Gbps | > 10 Gbps | > 10 Gbps | > 10 Gbps | GTH 16.3Gb/s GTY 30.5Gb/s Transceivers | GTH 16.3Gb/s GTY 30.5Gb/s Transceivers | GTH 16.3Gb/s GTY 32.75Gb/s Transceivers | GTY 32.75Gb/s Transceivers |
Size | The PCB width is (preferably) 65 mm (2.56’’) | 47.5x47.5 mm | 52.5 x 52.5 mm | 42.5 x 42.5 mm | 52.5 x 52.5 mm | |||
Cost | 40 k$ | 50-70 k$ | 6-10 k$ | 60-110 k$ |
*Done considering 1% Occupancy instead of maxing out the transceivers
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ePixUHR 140k 2x2 Detector SystemSparkPix S – 500k 2 x 2 ASIC Detector SystemSparkPix S 2M 4x4 Detector System |
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Requirement | Parameters | ||
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Power supply | 24V consistent with the HR detector | ||
Mechanical size | We would like to match the ePixHRM board dimensions to reuse cooling Side entrance detector
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Digital board | 2.56x5.265" | ||
Power and communication | 2.56x5.240" | ||
Carrier | 2.56x1.95 | Can we do it smaller? What is the minimum amount of components that need to leave in this board | |
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TOTAL = 13 * 4(n.Asics) + 9 + 70 + 30 = 161 out of 96 HD, 416 HP |
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Resources used: 32+12 = 44 GTH Discarding the extra 4 spares we can only use GTH signals, without the requirement of separate MGTY supplies. Even if we run the Amphenol Transceivers at the GTH speed (16.3Gbps), one transceiver gives us 179 Gbps (16.3 Gbps * 11 lanes) of bandwidth, which is enough for the 160Gbps expected by the 2x2 detector |
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For single ended → check the electrical specification |
Functionality | IO type | Quantity | switching specification |
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ASIC control (GR, ...) | 2.5V SE | Static | |
SUGOI | |||
SACI | |||
DATA | CLM? | 40 + spares? | 10Gbps |
System IO | |||
transceiver | 25Gbps | ||
supporting electronics | |||
enablels for power | |||
Slow ADC (current and voltage monitors, temperature sensors...) | |||
HS ADC | |||
serial number | |||
HS DAC | |||
Lower priority needs (R&D on system) | |||
FPGA to FPGA interconnection | requires GT+specific connector | ||
Goal is to have a decision on the FPGA package and family.
Kintex Ultrascale+ vs Virtex?
Ideal is to reuse the 300Gbps Leap On transceiver from Amphenol, unless we find a replacement that operates with single mode power supply.
Needs to be FR408HR or better
GT to the ASICs
GT to the transceivers
Power drops
Functionality | IO type | Quantity | Observations |
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carrier to digital board | 1 | Can we use smaller connectors since the number of data IOs per ASIC reduces from 24 to 10? | |
Digital to Power and communication | 1 | ||
Power communication to external power supply | 1 |
Notes: