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| Requirement | ePixUHR | SparkPix-S | SparkPix-ED  |
|---|---|---|---|
| frame rate | 100kfps | 1Mfps | 1Mfps |
| Power supplies | 2.5V Analog 1.3V (AS/DS/IO) | 2.5V Analog 1.3V (AS/DS/IO) 0.6V (Current sink!) | 1.2V (AS/DS/IO) |
| Power for each supply | ePixUHR - 35 kHz | SparkPix-S: supply/ground and power consumption | t.b.d. |
| Number of GT IOs per ASIC | 8 (outputs) | 8 (outputs) 1 clock in | t.b.d |
| Expected I/O speed | 5.25 Gb/s | 5.25 Gb/s | 10 Gb/s |
Total data bandwidth | 42 Gbit/s | 38 Gbit/s | |
FPGA Selection
ePixUHR 140k 2x2 Detector Specs | ePixUHR 1M 6x6 Detector Specs | SparkPix-S 2M 4x4 Detector Specs |
Target (2x2 Detector)
2MPix (sparkPix-s)
XCVU160 (-C2104) Virtex |
Ultrascale | KU15P (-A1760) Kintex Ultrascale+ | VU13P (-A2577) VirtexUltrascale+ |
General IO (HD |
, HP |
) | 52 HD, 364 HP | 96 HD, 416 HP | 0 HD, 448 |
HP |
High Speed IO (GTH/GTY) |
≥ 36 (32 outputs + 4 spares)
288
52
44
0
IO (GTY)
≥ 12 (Transceivers PGP)
60(72 for 6 transceivers)
52
32
128
- ASIC data: 32 = 8 lanes * 4 ASIC - Spare outputs : 4 - PGP communication: 12 = 12* 160 Gbps/ 275Gbps (1 Amphenol Transceiver) Total: 48 High Speed IOs | - ASIC data: 288 = 8 lanes * 36 ASIC - Spare outputs : 0 - PGP communication: 72 = 12* 1.44 Tbps/ 275Gbps (6 Amphenol Transceivers) Total: 360 High Speed IOs | - ASIC data: 128 = 8 lanes * 16 ASIC - Spare outputs : 0 - PGP communication: 36* = 12* 640 Gbps/ 275Gbps (3 Amphenol Transceivers) Total: 164 High Speed IOs | 104 (52 GTH/52 GTY) | 76 (44 GTH/32 GTY) | 128 (0 GTH/128 GTY) | |
Total Block RAM | 115.2 Mb | 34.6 Mb | 94.5 Mb | |||
UltraRam, HBM | None, None |
36 Mb, None | 360 Mb, None | |||||
Transceiver Speed (GTH, GTY) | > 10 Gbps | > 10 Gbps | > 10 Gbps | GTH 16.3Gb/s GTY 30.5Gb/s Transceivers | GTH 16.3Gb/s GTY 32.75Gb/s Transceivers | GTY 32.75Gb/s Transceivers |
Size | The PCB width is (preferably) 65 mm (2.56’’) | 47.5x47.5 mm | 42.5 x 42.5 mm | 52.5 x 52.5 mm | ||
Cost | 40 k$ | 6-10 k$ | 60-110 k$ |
Communication
*This can probably become 24 and done with 2 transceivers modules if the throughput is lower.
E.g. considering a 1% occupancy we get: 2Mpx * 24 bit * 1MHz * 66/64 * 1% = 495 Gbps
System level
| Requirement | Parameters | ||
|---|---|---|---|
| Power supply | 24V consistent with the HR detector | ||
| Mechanical size | We would like to match the ePixHRM board dimensions to reuse cooling Side entrance detector
|
| |
| Digital board | 2.56x5.265" | ||
| Power and communication | 2.56x5.240" | ||
| Carrier | 2.56x1.95 | Can we do it smaller? What is the minimum amount of components that need to leave in this board | |
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