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• for hsd Matt says that the firmware supports overlapping waveforms, so if gate_ns is larger than the trigger rate it should behave correctly.  we tried to make gate_ns large enough to do that , but DMA buffer sizes were too small to support that at 71kHz: we received a clear crash/error in the associated hsd log file when we exceeded the DMA buffer size.  To do: we should try at 1MHz where we can get overlapping waveformsby running at 1MHz and setting both raw/fex gate_ns to 3000ns.  Both appeared to behave correctly, until we set the fex threshold low.
• for piranha if we made gate_ns larger than trigger rate got deadtime from the correct detector and disable timed out only for that detector.  my guess is that we dropped triggers so would be off-by-one, but don't know that for sure

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Introduced sleep(10000) in piranha _event() method.  Chaotic deadtime not from the piranha(!) .  Needs to be understoodbut from epicsarch.  daqpipes showed a backup in the pre-fex-worker piranha buffers, but we think the clearest indication of the source of the problem is a low "%BatchesInFlight" to the TEB.  This perhaps makes sense, because the TEB is "eager" to receive the batches from the bottleneck detector.

Also see TEB crashes where it is unclear who is the bottleneck.

Bad HSD FEX Params

Did this by setting low thresholds in tmo hsd_3 when there was too much data saw a low "%BatchesInFlight" to the TEB which is perhaps the clearest indication of the problem.  Can also get TEB crashes (where it is unclear who is responsible) and for hsd_5 with low threshold we saw DMA buffer-overflow crashes (where it is clear who is responsible).

L0Delay

To be done

Timing System kcu1500 (or "sim")

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