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Thanks for looking into this, Chris.  The only thing I’ve been able to come up with on a quick look is that the time is maybe going into setting up the memory region for the DRP to share the event with the MEBs.  I think this is mostly libfabric manipulating the MMU for this already allocated space (the pebble).  Is the event buffer size maybe particularly large compared to the other DRPs?  I’m guessing that since it’s an Andor, maybe 8 MB?  Not sure what ‘vls’ does to it.  If the trigger rate for this DRP isn’t high (10 Hz?), we could maybe speed this step up by lowering the number of DMA buffers so that fewer MMU entries are needed.

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DAQ Misconfiguration Issues

Default plan: high-rate detectors get L0Delay 100, low-rate detectors get L0Delay 0.  Lower L0Delay numbers increase pressure on buffering which can result in deadtime and dropped Disable-phase2 transitions.

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• in hsdpva "full_event" (currently 8) and "full_size" (currently 2048): these are "remaining" buffers, so when either of these ("or") drops below this value then deadtime is asserted. need two parameters because the FEX is variable length.

epixhr

• to be determined determined

Other Misconfigurations

May 19, 2023: working meeting monarin, melchior, valmar, cpo introduced deliberate misconfigurations in DAQ to understand behavior

gate_ns

• for hsd Matt says that the firmware supports overlapping waveforms, so if gate_ns is larger than the trigger rate it should behave correctly.  we tried to make gate_ns large enough to do that, but DMA buffer sizes were too small to support that at 71kHz: we received a clear crash/error in the associated hsd log file when we exceeded the DMA buffer size.  To do: we should try at 1MHz where we can get overlapping waveforms
• for piranha if we made gate_ns larger than trigger rate got deadtime from the correct detector and disable timed out only for that detector.  my guess is that we dropped triggers so would be off-by-one, but don't know that for sure

Slow DRP FEX

Introduced sleep(10000) in piranha _event() method.  Chaotic deadtime not from the piranha(!).  Needs to be understood.

L0Delay

To be done

Timing System kcu1500 (or "sim")

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With RawBuffers.BuffLen set to 32 (samples, I'm guessing), a 1 MHz run with 0 deadtime succeeded.  Also Disable went through.

Deadtime Issues

In the latest wave8 front-end-board firmware (2.4.x) there is a new DataPathCtrl register.  This has two bits that enable deadtime to the XPM.  It looks like it currently defaults to 0x3 (both controls and daq data paths can assert deadtime) and we think it should be set to 0x2 (only daq pth can assert deadtime).  We believe the controls-side will drop in units of “entire events” so 0x2 should be fine for controls.

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