Page History
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| Module | Description | Simulation | Test in hardware |
|---|---|---|---|
| RegisterControlDualClock | VR2 (6V EN), VR3 (1.8V), VR4 (3.3V DIG) | Tested waveform to ASICs and AXILite RW | Tested multiplexer to digital output, analog and digital serial ID, AXILite RW |
| TrigControlAxi | Tested software trigger to generate waveforms to ASICs | ||
| AXiStreamRepeater | Not tested | ||
| DigitalAsicStreamAxiV2 | Not tested | ||
| AxiStreamBatcherEventBuilder | Not tested | ||
| AxiLiteSaciMaster | U22/U20/U21 (level shifters) | ||
| AppClk | - | ||
| AppDeser | Not tested | ||
| PwrCtrl | Tested 6V, analog and digital enable with testpoints | ||
| DAC - Max5443 | U12/U16 (level shifter), U79 (DAC) | Tested with testpoint | |
| DAC - DacWaveformGenAxi | U76/U77/U75 | Tested waveform | Tested with testpoint single writes |
| AdcMon | U5 (Slow ADC - DIG) U10/U12/U14(Slow ADCs AN) | ||
| TimingRx | - | ||
| Chip scope pro | error after loading bit stream | ||
| SI5345 Jitter cleaner | Not tested | Device ID registers seem to be readable. Logic in FPGA still depend on lol output, so AXI locks after configuring. | |
| PROM | U13 (PROM) | Boot from PROM | |
| JTAG | J2 | Tested by writing bitstream | |
| Clock splitter | U60/U59/U61 | ||
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