Page History
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| Register name | Address | Access | Bits | Alias | Description |
|---|---|---|---|---|---|
Control | 0x0 | RW | 0 | SW Trigger Enable | Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again. |
| 1 | Cascade Trigger enable | Enabling/disabling cascaded trigger
| |||
| 2 | Auto Rearm HW Trigger | Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger
| |||
| 3 | Arm HW Trigger | Arms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register. | |||
| 4 | Trigger Clear Status | Trigger status will be cleared (On the rising edge). | |||
| 5 | Daq Mode | Select the data acquisition mode ( Stream stops if Error occurs )
| |||
| 6 | Packet Header Enable | Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only)
| |||
| 7 | SW Freeze Buffer | Freezes all enabled circular buffers | |||
| 8 | HW Freeze Buffer Enable | Enabling/disabling hardware freeze buffer request
| |||
| Status | 0x1 | RO | 0 | Software Trigger Status | Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ). |
| 1 | Cascade Trigger Status | Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ) | |||
| 2 | HW Trigger Status | Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ) | |||
| 3 | HW Trigger Armed Status | Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs ) | |||
| 4 | Combined Trigger Status | Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] ) | |||
| 5 | Freeze Buffers Status | Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] ) | |||
| Decimation | 0x2 | RW | 15:0 | Decimation Rate Divisor | Sample rate divider (Decimator):
|
| DataSize | 0x3 | RW | 31:0 | Data Buffer Size | Number of 32-bit words to forward at each trigger (Ignored in continuous mode) (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header). |
| TimeStamp | 0x4 | RO | 31:0 | Timestamp[31:0] | Timestamp [31:0] - secPastEpoch |
| 0x5 | RO | 31:0 | Timestamp[63:32] | Timestamp [63:32] - nsec | |
| BSA | 0x6 | RO | 31:0 | bsa(0) | edefAvgDn |
| 0x7 | 31:0 | bsa(1) | edefMinor | ||
| 0x8 | 31:0 | bsa(2) | edefMajor | ||
| 0x9 | 31:0 | bsa(3) | edefInit | ||
| TrigCount | 0xA | RO | 31:0 | Trigger Count | Counts valid data acquisition triggers |
| DbgInputValid | 0xB | RO | 31:0 | Debug Input Valid | All DaqMux AXI input streams valid signals |
| DbgLinkReady | 0xC | RO | 31:0 | Debug Link Ready | All DaqMux AXI input streams ready signals |
| InputMuxSel | 0x10 | RW | 4:0 | Input Mux Select[0] | 0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) Test mode will output counter data |
| 0x11-0x1E | 4:0 | Input Mux Select[1]-[14] | |||
| 0x1F | 4:0 | Input Mux Select[15] | |||
| DaqStatus | 0x20-0x2F (one register for each of the 16 (enabled) lanes) | RO | 0 | Stream Pause | (rxAxisCtrlArr_i port signal) Raw diagnostic stream control pause (Waveform engine bufferDone signal. When an AXI frame is completely written to DRAM, this bit is set) |
| 1 | Stream Ready | Debug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal) | |||
| 2 | Stream Overflow | (rxAxisCtrlArr_i port signal) Raw diagnostic stream control Overflow (set to 0 in waveform engine) | |||
| 3 | Stream Error | Debug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped) | |||
| 4 | Data source ready | Debug signal: The data source is ready. If not, DaqMux sets error signal to 1 | |||
| 5 | Stream Enable | Debug signal: Output stream enabled | |||
| 31:6 | Frame Count | Number of 4096 word frames sent | |||
| DataFormat | 0x30-0x3F (one register for each of the 16 (enabled) lanes) | RW | 4:0 | Sign Bit Position | Indicating sign extension point (all bits after sign bit will be overwritten with sign) |
| 5 | Data Width | Data width 32-bit or 16-bit
| |||
| 6 | Sign enable | Signed/unsigned
| |||
| 7 | Decimation Averaging Enable | Decimation Averaging
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