Page History
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Firmware
| Task | Description | Status | Date | Owner |
|---|---|---|---|---|
| AxiLiteCrossbar | Create a xbar for the ASICTOP module | done | Dawood | |
| Port ASIC control module | use Register control as copy and paste into the new module | done | Dawood | |
| Port trigger module | copy from epix-hr-single-10k | done | Dawood | |
| Simulate | Simulate both modules | done | Dawood | |
| axilite address space | Define address space for the ASIC top | started | Dawood | |
| axiStreamRepeaters | Repeaters for the timing information (x5) | Done |
| Dawood |
| axiStreamBatcher | Creates the data package with image and timing info (x5) | Done |
| Dawood |
| DigitalAsicStreamV2 | Port to 2m and increase number of ASICs to 4 | Done |
| Dawood |
| Synthesis | Make sure design synthesizes completed, update constraints if needed. | Done |
| Dawood |
| Software | Complete companion device/register definition, if missing. | Done |
| Dawood |
| Hardware deployment | Test HW/SW register access | Dawood/Dionisio | ||
| ASIC Model | Port from simulation test bench an ASIC model to a new HDL entity that will mimic the ASIC data path. Needs a data length counter to send one frame per SRO. Map all IO to the ASIC even though some will not be used for this simulation. | |||
| DigitalAsicSttreamV3 | Create internal module to de-interleave the images | Dawood |
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