Page History

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Add proposed block diagram to implement the aforementioned requirements (update figure below)

List of tracking tasks

• System level
  • Over the fiber programability
  • XVC infrastructure
  • Insert timing receiver modules and LCLS-II timing receiver
• ASIC Modules
  • Integrate of ASIC controls and configuration
  • Integrate of data receiver and decoder
  • Development of data packet and event builder
  • Serial number
• Digital board infrastructure
  • PGP4 comminication
  • PLL configuration
  • Environmental monitoring
  • Serial number
• Analog board infrastructure
  • ASIC power supply control
  • ASIC analog monitoring subsystem
  • ASIC digital monitoring 
  • Serial number
• Software
  • Rogue tree definition
  • Data visualization
• Testing
  • Test each individual module read and write registers
  • Test ALL 20 ASIC positions for configuration, control and data streaming
  • Stress test data frame rate generation
  • Test RUN trigger and DAQ trigger
  • Test all monitor sensors
  • Test all DACs
  • Test high speed DAC with ASIC ADC
  • Test timing trigger with multiple quads