Digital trigger output for SSA (1 channel, 0V - 3.3V).
Will need modulator (2 channel), interlock (x channel), and debug (1 channel) output triggers in the future (not sure on specifications, discuss RadioBeam).
Digital inputs TBD with RadioBeam
Chao's LLRF Data Converter Characterization
Trying to reocver/understand Dan's previous work
Evaluation tool is limited to running 1.6us samples meaning stability is too low (want ~5us)
Test: Signals from RFSOC loaded to DAC and looped back to ADCs. ADC output processed in Matlab (excludes op-amp downcoverter)
Image Added
(Bo) Could do an FFT to check there's anything extra going on
Next test to include up/down converters
Chao RFSoC SOM Purchase Proposal
XRF16: 26 weeks, $30k/SOM + $6k/carrier. Will want 6x each ($216k)
Ryan+Stephen: Budget plan is incomplete and Schedule is on existent
We need a charge number for work on this project
8/29/2022
Bo had her first meeting with the high power people last week
Briefly discussed progress and later met with Radiobeam to discuss technical parts and RFSoC
Most of their FPGA experience is Larry Doolittle
We should consider having Radiobeam lead the hardware architecture design. Should discuss further with Ryan
Wedriveit but they do the documentation
Chao and Larry need to document the phase reference (LMK/LMX) clock distribution scheme
Larry needs to complete importing Dan Van Winkle's .XCI and adding LMX to rogue software for next week and make sure it syncs with the ADCs and DACs
Chao/Kukhee needs to define the exact interface between ADC/DAC and LLRF DSP
Chao/Kukhee needs to define the specification for the LLRF DSP
Chao will present the RFSoC SOM design trade study for next week's meeting (Note that Monday is a holiday)
Recommend buying 16 channel SOM, but will need to provde a justification as it is high price (>$100k) and long lead time (>26week)
Stephen to start taking meeting notes and review Ryan's Smartsheet stuff prior to official release of budget/schedule