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| Category | Name | Direction | Clock domain | Width | Description | |
|---|---|---|---|---|---|---|
Clock & reset logic | axiClk | Input | - | 1 | AXI Lite clock | |
| axiRst | Input | axiClk | 1 | AXI Lite reset | ||
| devClk_i | Input | - | 1 | Development clock | ||
| devRst_i | Input | Synced to devClk_i in DaqMux (for some reason) | 1 | Development logic reset | ||
| wfClk_i | Input | - | 1 | Ouput lanes' clock | ||
| wfRst_i | Input | wfClk_i | 1 | Output lanes' reset | ||
DaqMux control signals and timing information | trigHw_i | Input | Synced to devClk_i in DaqMux | 1 | Trigger signal to start the DaqMux streaming
| |
| trigCasc_i | Input | Synced to devClk_i in DaqMux | 1 | Cascaded trigger input. Can be used along with trigHw_i when enabled in the register file
| ||
| trigCasc_o | Output | devClk_i | 1 | Output trigger signal connected to the SW Trigger Enable control register
| ||
| armCasc_i | Input | Synced to devClk_i in DaqMux | 1 | Cascaded trigger Arm. Arms the trigger and prepares DaqMux for trigger arrival
| ||
| armCasc_o | Output | devClk_i | 1 | Output cascade signal connected to the Arm HW Trigger control register
| ||
| freezeHw_i | Input | Synced to devClk_i in DaqMux | 1 | Adds invalid flag to the streams that are forwarded, and they will be discarded in one of the posterior blocks in the pipeline
| ||
| timeStamp_i | Input | Synced to devClk_i in DaqMux | 64 | Time stamp coming from the AMC carrier core | ||
| bsa_i | Input | Synced to devClk_i in DaqMux | 128 | BSA information coming from the AMC carrier core | ||
| dmod_i | Input | Synced to devClk_i in DaqMux | 192 | Dmod timing information coming from the AMC carrier core | ||
AXI Lite register memory mapped interface for reading and writing to register file | axilReadMaster | Input | axiClk | 1 | AXI Lite record containing Read Address channel
Read data channel
| |
| axilReadSlave | Output | axiClk | 1 | AXI Lite record containing Read Address channel
Read data channel
| ||
| axilWriteMaster | Input | axiClk | 1 | AXI Lite record containing Write address channel
Write data channel
Write ack channel
| ||
| axilWriteSlave | Output | axiClk | 1 | AXI Lite record containing Write address channel
Write data channel
Write ack channel
| ||
Input lane array - data valid based | sampleDataArr_i | Input | devClk_i | N_DATA_IN_G | Input data stream array of 32-bit words | |
| sampleValidVec_i | Input | devClk_i | N_DATA_IN_G | Input valids with each valid corresponding to the respective stream in that cycle | ||
| linkReadyVec_i | Input | devClk_i | N_DATA_IN_G | Indicate that the stream source is ready. If is 0, the DaqMux sets the Stream Error control register to 1. | ||
| rxAxisMasterArr_o | Output | wfClk_i | N_DATA_OUT_G | AXI compliant output data stream array of 32-bit words. Nonetheless, the type of rxAxisMasterArr_o is defined as follows in the AxiStreamPkg.vhd file
| |
| rxAxisSlaveArr_i | Input | wfClk_i | N_DATA_OUT_G | AXI streams data ready signals | ||
| rxAxisCtrlArr_i | Input | Synced to devClk_i in DaqMux | N_DATA_OUT_G | AXI stream control signals as follows
If pause is 1, the DaqMux will not start and error is set. Represents status(DONE_C) signal in the AxiStreamDmaRingWrite module of the waveforEngine. Not clear what is the meaning of this flag. Found this comment in that module
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- freezeHw_i
- trigHw_i
- DAC input signals
- Data - sampleDataArr_i[13:7] to sampleDataArr_i[13] : AppCore dacValues[6:0] to dacValues[7]their valids
- Valids - sampleValidVec_i[13:7] to sampleValidVec_i[13]: AppCore dacValids[6:0] to dacValids[6]
- Debug input signals:
- Data - sampleDataArr_i[17:14] to sampleDataArr: AppCore debugValues[3:0]
- Valid - sampleValidVec_i[17:14] : AppCore debugValuesdebugValids[3:0] to debugValues[3]sampleValidVec_i[14] to sampleValidVec_i[17] : AppCore debugValids[0] to debugValids[6
LinkReady signals: Mapped to valids of all stream except for debug
- LinkReady[17:14]: 4'hF
- LinkReady[13:7]: dacValids[6:0]
- LinkReady[6:0]: adcValids[6:0]
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