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Register name

Address

AccessBitsPV NameAliasDescription

Control

0x0RW

0


SW Trigger Enable

Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again.

1${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRGCascade Trigger enable

Enabling/disabling cascaded trigger

  • '0' - Disable Cascaded Trigger
  • '1' - Enable Cascaded Trigger
2${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARMAuto Rearm HW Trigger

Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger

  • '0' - Disabled (has to be armed with bit3 otherwise disabled)
  • '1' - Enabled
3${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRGArm HW TriggerArms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register.
4${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGSTTrigger Clear StatusTrigger status will be cleared (On the rising edge).
5${DEVICE}:DAQMUX${DAQMUX#}_DAQMODEDaq Mode

Select the data acquisition mode ( Stream stops if Error occurs )

  • '0' - Trigger mode - Normal DAQ mode
    • Has to be triggered to start every time
  • '1' - Continuous mode - The data is framed and continuously streamed out after enabled. (Still requires a trigger to start)
    • Disable the stream to stop
6${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADERPacket Header Enable

Add 128-bit header (otherwise only data will be inserted)(Applies only to Triggered mode only)

  • '0' - Disabled
  • '1' - Enabled
7${DEVICE}:DAQMUX${DAQMUX#}_FRZBUFSW Freeze Buffer Freezes all enabled circular buffers
8${DEVICE}:DAQMUX${DAQMUX#}_HWFRZHW Freeze Buffer Enable

Enabling/disabling hardware freeze buffer request

  • '0' - Disabled
  • '1' - Enabled
Status0x1RO

0


Software Trigger Status

Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).

1
Cascade Trigger StatusCascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
2
HW Trigger StatusHardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
3
HW Trigger Armed StatusHardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
4
Combined Trigger StatusCombined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
5
Freeze Buffers Status Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation0x2RW15:0${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIVDecimation Rate Divisor

Sample rate divider (Decimator):

  • Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12)
  • Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).
  • Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).


DataSize0x3RW
${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZEData Buffer Size

Number of 32-bit words to forward at each trigger (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header).

TimeStamp0x4RO31:0${DEVICE}:DAQMUX${DAQMUX#}_TS_NSECTimestamp[31:0]Timestamp [31:0] - secPastEpoch
0x5RO31:0${DEVICE}:DAQMUX${DAQMUX#}_TS_SECTimestamp[63:32]Timestamp [63:32] - nsec
BSA0x6RO31:0
bsa(0)

edefAvgDn

0x731:0
bsa(1)edefMinor
0x831:0
bsa(2)edefMajor
0x931:0
bsa(3)edefInit
TrigCount0xARO31:0${DEVICE}:DAQMUX${DAQMUX#}_TRGCNTTrigger CountCounts valid data acquisition triggers
DbgInputValid0xBRO31:0${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALIDDebug Input ValidAll DaqMux AXI input streams valid signals 
DbgLinkReady0xCRO31:0${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDYDebug Link ReadyAll DaqMux AXI input streams ready signals
InputMuxSel0x10RW4:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0

Input Mux Select[0]

0x1x: Stream x: Channel select Multiplexer 

0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29)

Test mode will output counter data

0x114:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1

Input Mux Select[1]
0x124:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2

Input Mux Select[2]
0x134:0

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3

${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3

Input Mux Select[3]
0x14-0x1F
-Not used
DaqStatus0x20-0x23RO0

${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3)

Stream Pause

Debug flag: Raw diagnostic stream control pause (Waveform engine bufferDone signal. When a complete a new AXI frame is written to DRAM, this bit is set)

1${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3)Stream ReadyDebug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal)
2${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3)Stream OverflowDebug flag: Raw diagnostic stream control Overflow (set to 0 in waveform engine)
3${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3)Stream ErrorDebug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
4${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3)Input Data validDebug signal: The incoming data is Valid (Usually connected to JESD valid signal).
5${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3)Stream EnableDebug signal: Output stream enabled
31:6${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3)Frame CountNumber of 4096 byte frames sent
024-0x2F

Not used
DataFormat0x30-0x33RW4:0${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3)Format Sign WidthIndicating sign extension point



5${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3)Format Data Width

Data width 32-bit or 16-bit

  • '0' : 32-bits
  • '1' : 16-bits



6${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3)Format Sign

Signed/unsigned

  • '0' : Unsigned
  • '1' : Signed



7${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3)Decimation Averaging

Decimation Averaging

  • '0' : Disable
  • '1' : Enable




${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQ
A sequence setting Software Trigger Enable to 1 then 0

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