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The DaqMux system is shown in Figure 1. The DaqMux component of the FPGA in the application board of the ATCA allows the user to choose to stream up to four streams to the software (IOC) of the input streams routed to the DaqMux. All ATCA projects are configured to have two DaqMuxes, one associated with each AMC daughter board, summing a total of 8 streams routed to software. Each of the two DaqMux has 20 streams of data routed to its input. One may assume that the DaqMux only performs multiplexing of continuous streams as denoted by the component's name, but that is not only the case. The DaqMux not only allows continuous (continuous mode) streaming of multiplexed streams, but also it allows that a fixed size of the multiplexed input streams is burst upon a reception of a trigger (trigger mode) from the timing core on the FPGA firmware. The DaqMux functionality can be summarized as follows:
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Acquisition can be either continuous, single, or single many times. In all three cases a trigger is needed. In the continuous case (i.e. continuous mode), at every trigger, the DaqMux acquires a number of configured bytes (i.e. Frame count) and sends them up to software. In single acquisition (trigger mode), the DaqMux is armed only once, and a number of configured bytes (i.e. Frame count) is sent to software with or without a header. Single many times acquisition is just a sub-case of single acquisitions, however; auto re-arm is enabled, and everytime there is a trigger a number of configured bytes (i.e. Frame count) is sent to software with or without a header.
The DaqMux functionality can be summarized as follows:
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The Graphical user interface of a DaqMux is shown in Figure 2. The main graphical user interface for configuring the DaqMux is quite simple and masks a lot of the DaqMux configurations. It only allows the user to perform the following
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Source | Description |
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${MuxIn#} : Test | Test pattern stream (simple counter data) |
${MuxIn#} : Disable | Disable stream |
${MuxIn#} : ADC${ADC#} | ADC Source not connected |
${MuxIn#} : DAC${DAC#} | DAC Destination not connected |
${MuxIn#} : DBG${DBG#} | Debug streams - application specific and used for debugging (e.g. not used in GMD firmware) |
${MuxIn#} : RF IN ${RF#} : ADC${ADC#} FP | Stream data coming through AMC front panel physical port RF IN ${RF#} through ADC${ADC#} |
${MuxIn#} : RF OUT MON : ADC${ADC#} FP | Stream data coming through AMC front panel physical port RF OUT MON through ADC${ADC#} |
${MuxIn#} : DC IN ${DC#} : ADC${ADC#} FP | Stream data coming through AMC front panel physical port DC IN ${DC#} through ADC${ADC#} |
${MuxIn#} : TRIG MON : ADC${ADC#} (FP) | Stream data coming through AMC front panel physical port TRIG MON through ADC${ADC#} |
${MuxIn#} : CLK PLL DAC : DAC${DAC#} | Stream the applied voltage to the voltage controlled oscillator transmitted through DAC${DAC#} |
${MuxIn#} : LO PLL DAC : DAC${DAC#} | Stream the applied LO signal mixed with RF sinal to get an IF signal transmitted through DAC${DAC#}. This is specific to the LLRF applcation |
${MuxIn#} : DAC OUT : DAC${DAC#} (FP) | Stream data coming out through AMC front panel physical port DAC OUT through DAC${DAC#} |
${MuxIn#} : RF OUT : DAC${DAC#} (FP) | Stream data coming out through AMC front panel physical port RF OUT through DAC${DAC#} |
The DaqMux settings setup page allows the user to fine control the DaqMux by reading and writing to and from the DaqMux registers. The DaqMux settings setup GUI is shown in Figure 5.
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The DaqMux settings setup contains 3 tabs:
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is specific to the LLRF applcation | |
${MuxIn#} : DAC OUT : DAC${DAC#} (FP) | Stream data coming out through AMC front panel physical port DAC OUT through DAC${DAC#} |
${MuxIn#} : RF OUT : DAC${DAC#} (FP) | Stream data coming out through AMC front panel physical port RF OUT through DAC${DAC#} |
The DaqMux settings setup page allows the user to fine control the DaqMux by reading and writing to and from the DaqMux registers and some CPSW sequencers (program sequences of writings to a register). The DaqMux settings setup GUI is shown in Figure 5.
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The DaqMux settings setup contains 3 tabs:
The possible functionalities that can be performed using the DaqMux settings tab are as follows: (Note if the configuration name in GUI differs from the control register Alias, the mapped Alias is shown between parenthesis)
A full list of all PVs and their Register mapping and description can be seen in Table 2. This table was extracted from the firmware YAML file of the DaqMux. Registers with a blank PV name are not exported to EPICS. PVs with not register names are generated in CPSW libraries, and eventually control registers by applying a sequence of values to them.
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Register name | Address | Access | Bits | PV Name | Sub-nameAlias | Description |
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Control | 0x0 | RW | 0 | Software SW Trigger Enable | Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again. | |
1 | ${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRG | Cascade Trigger enable | Enabling/disabling cascaded trigger
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2 | ${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARM | Auto Rearm Hw HW Trigger | Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger
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3 | ${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRG | Arm HW Trigger | Arms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register. | |||
4 | ${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGST | Trigger Clear Status | Trigger status will be cleared (On the rising edge). | |||
5 | ${DEVICE}:DAQMUX${DAQMUX#}_DAQMODE | DAQ Daq Mode | Select the data acquisition mode ( Stream stops if Error occurs )
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6 | ${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADER | Packet Header Enable | Add 128-bit * header (otherwise only data will be inserted)(Applies only to Triggered mode only)
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7 | ${DEVICE}:DAQMUX${DAQMUX#}_FRZBUF | Sw SW Freeze Buffer | Freezes all enabled circular buffers | |||
8 | ${DEVICE}:DAQMUX${DAQMUX#}_HWFRZ | Hw HW Freeze Buffer MaskEnable | Mask for enablingEnabling/disabling hardware freeze buffer request
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Status | 0x1 | RO | 0 | Software Trigger Status | Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ). | |
1 | Cascade Trigger Status | Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ) | ||||
2 | HW Trigger Status | Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ) | ||||
3 | HW Trigger Armed Status | Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs ) | ||||
4 | Combined Trigger Status | Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] ) | ||||
5 | Freeze Buffers Status | Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] ) | ||||
Decimation | 0x2 | RW | 15:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIV | Decimation Rate Divider | Sample rate divider (Decimator):
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DataSize | 0x3 | RW | ${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZE | Data Buffer Size | Number of 32-bit words (if enabled header will be included in the first 14 words of data).
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TimeStamp | 0x4 | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TS_NSEC | Timestamp[31:0] | Timestamp [31:0] - secPastEpoch |
0x5 | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TS_SEC | Timestamp[63:32] | Timestamp [63:32] - nsec | |
BSA | 0x6 | RO | 31:0 | bsa(0) | edefAvgDn | |
0x7 | 31:0 | bsa(1) | edefMinor | |||
0x8 | 31:0 | bsa(2) | edefMajor | |||
0x9 | 31:0 | bsa(3) | edefInit | |||
TrigCount | 0xA | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_TRGCNT | Trigger Count | Counts valid data acquisition triggers. |
DbgInputValid | 0xB | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALID | Debug Input Valid Bus | All DaqMux AXI input streams valid signals |
DbgLinkReady | 0xC | RO | 31:0 | ${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDY | Debug Link Ready | All DaqMux AXI input streams ready signals |
InputMuxSel | 0x10 | RW | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0 | Input Mux Select[0] | 0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) Test mode will output counter data |
0x11 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1 | Input Mux Select[1] | |||
0x12 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2 | Input Mux Select[2] | |||
0x13 | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3 | Input Mux Select[3] | |||
0x14-0x1F | - | Not used | ||||
DaqStatus | 0x20-0x23 | RO | 0 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3) | Stream Pause | Debug flag: Raw diagnostic stream control pause (Waveform engine bufferDone signal. When a complete a new AXI frame is written to DRAM, this bit is set) |
1 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3) | Stream Ready | Debug flag: Raw diagnostic stream control Ready (Waveform engine FIFO output stream ready signal) | |||
2 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3) | Stream Overflow | Debug flag: Raw diagnostic stream control Overflow (set to 0 in waveform engine) | |||
3 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3) | Stream Error | Debug flag: Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped) | |||
4 | ${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3) | Input Data valid | Debug signal: The incoming data is Valid (Usually connected to JESD valid signal). | |||
5 | ${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3) | Stream Enable | Debug signal: Output stream enabled | |||
31:6 | ${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3) | Frame Count | Number of 4096 byte frames sent | |||
024-0x2F | Not used | |||||
DataFormat | 0x30-0x33 | RW | 4:0 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3) | Format Sign Width | Indicating sign extension point |
5 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3) | Format Data Width | Data width 32-bit or 16-bit
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6 | ${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3) | Format Sign | Signed/unsigned
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7 | ${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3) | Decimation Averaging | Decimation Averaging
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${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQ | A sequence setting Software Trigger Enable to 1 then 0 |
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Not in original requirements document | |
Not exported to EPICS |
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