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Source	Description
${MuxIn#} : Test	Test pattern stream (simple counter data)
${MuxIn#} : Disable	Disable stream
${MuxIn#} : ADC${ADC#}	ADC Source not connected
${MuxIn#} : DAC${DAC#}	DAC Destination not connected
${MuxIn#} : DBG${DBG#}	Debug streams - application specific and used for debugging (e.g. not used in GMD firmware)
${MuxIn#} : RF IN ${RF#} : ADC${ADC#} FP	Stream data coming through AMC front panel physical port RF IN ${RF#} through ADC${ADC#}
${MuxIn#} : RF OUT MON : ADC${ADC#} FP	Stream data coming through AMC front panel physical port RF OUT MON through ADC${ADC#}
${MuxIn#} : DC IN ${DC#} : ADC${ADC#} FP	Stream data coming through AMC front panel physical port DC IN ${DC#} through ADC${ADC#}
${MuxIn#} : TRIG MON : ADC${ADC#} (FP)	Stream data coming through AMC front panel physical port TRIG MON through ADC${ADC#}
${MuxIn#} : CLK PLL DAC : DAC${DAC#}	Stream the applied voltage to the voltage controlled oscillator transmitted through DAC${DAC#}
${MuxIn#} : LO PLL DAC : DAC${DAC#}	Stream the applied LO signal mixed with RF sinal to get an IF signal transmitted through DAC${DAC#}. This is specific to the LLRF applcation
${MuxIn#} : DAC OUT : DAC${DAC#} (FP)	Stream data coming out through AMC front panel physical port DAC OUT through DAC${DAC#}
${MuxIn#} : RF OUT : DAC${DAC#} (FP)	Stream data coming out through AMC front panel physical port RF OUT through DAC${DAC#}

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Register name	Address	Access	Bits	PV Name	Sub-name	Description
Control	0x0	RW	0		Software Trigger Enable	Triggers DAQ on all enabled channels. Must be set to 1, then set to 0 again.
			1	${DEVICE}:DAQMUX${DAQMUX#}_CSCDTRG	Cascade Trigger enable	Enabling/disabling cascaded trigger '0' - Disable Cascaded Trigger '1' - Enable Cascaded Trigger
			2	${DEVICE}:DAQMUX${DAQMUX#}_AUTOREARM	Auto Rearm Hw Trigger	Enabling/disabling hardware automatic trigger. If disabled it has to be rearmed by Arm Hw Trigger '0' - Disabled (has to be armed with bit3 otherwise disabled) '1' - Enabled
			3	${DEVICE}:DAQMUX${DAQMUX#}_ARMHWTRG	Arm HW Trigger	Arms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed using this register.
			4	${DEVICE}:DAQMUX${DAQMUX#}_CLRTRGST	Trigger Clear Status	Trigger status will be cleared (On the rising edge).
			5	${DEVICE}:DAQMUX${DAQMUX#}_DAQMODE	DAQ Mode	Select the data acquisition mode ( Stream stops if Error occurs ) '0' - Trigger mode - Normal DAQ mode Has to be triggered to start every time '1' - Continuous mode - The data is framed and continuously streamed out after enabled. (Still requires a trigger to start) Disable the stream to stop
			6	${DEVICE}:DAQMUX${DAQMUX#}_PACKETHEADER	Packet Header Enable	Add 128-bit *header (otherwise only data will be inserted)(Applies only to Triggered mode only) '0' - Disabled '1' - Enabled
			7	${DEVICE}:DAQMUX${DAQMUX#}_FRZBUF	Sw Freeze Buffer	Freezes all enabled circular buffers
			8	${DEVICE}:DAQMUX${DAQMUX#}_HWFRZ	Hw Freeze Buffer Mask	Mask for enabling/disabling hardware freeze buffer request '0' - Disabled '1' - Enabled
Status	0x1	RO	0		Software Trigger Status	Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).
			1		Cascade Trigger Status	Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
			2		HW Trigger Status	Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
			3		HW Trigger Armed Status	Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
			4		Combined Trigger Status	Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
			5		Freeze Buffers Status	Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation	0x2	RW	15:0	${DEVICE}:DAQMUX${DAQMUX#}_DECRATEDIV	Decimation Rate Divider	Sample rate divider (Decimator): Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12) Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1). Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).
DataSize	0x3	RW		${DEVICE}:DAQMUX${DAQMUX#}_BUFFSIZE	Data Buffer Size	Number of 32-bit words (if enabled header will be included in the first 14 words of data). Minimum size is 14 (the size of the header).
TimeStamp	0x4	RO	31:0	${DEVICE}:DAQMUX${DAQMUX#}_TS_NSEC	Timestamp[31:0]	Timestamp [31:0] - secPastEpoch
TimeStamp	0x5	RO	31:0	${DEVICE}:DAQMUX${DAQMUX#}_TS_SEC	Timestamp[63:32]	Timestamp [63:32] - nsec
BSA	0x6	RO	31:0		bsa(0)	edefAvgDn
	0x7		31:0		bsa(1)	edefMinor
	0x8		31:0		bsa(2)	edefMajor
	0x9		31:0		bsa(3)	edefInit
TrigCount	0xA	RO	31:0	${DEVICE}:DAQMUX${DAQMUX#}_TRGCNT	Trigger Count	Counts valid data acquisition triggers.
DbgInputValid	0xB	RO	31:0	${DEVICE}:DAQMUX${DAQMUX#}_DBGINPVALID	Debug Input Valid BusInput Valid bus for debugging	AXI streams valid signals (hardware specific)
DbgLinkReady	0xC	RO	31:0	${DEVICE}:DAQMUX${DAQMUX#}_DBGLNKRDY	Debug Link ReadyInput LinkReady bus for debugging	AXI streams ready signals (hardware specific)
InputMuxSel	0x10	RW	4:0	${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR0 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL0	Input Mux Select[0]	0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) Test mode will output counter data
	0x11		4:0	${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR1 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL1	Input Mux Select[1]
	0x12		4:0	${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR2 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL2	Input Mux Select[2]
	0x13		4:0	${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSELSTR3 ${DEVICE}:DAQMUX${DAQMUX#}_INPMUXSEL3	Input Mux Select[3]
	0x14-0x1F			-	Not used
DaqStatus	0x20-0x23	RO	0	${DEVICE}:DAQMUX${DAQMUX#}_STRMPAUSE(0-3)	Stream Pause	Raw diagnostic stream control Pause
			1	${DEVICE}:DAQMUX${DAQMUX#}_STRMRDY(0-3)	Stream Ready	Raw diagnostic stream control Ready
			2	${DEVICE}:DAQMUX${DAQMUX#}_STRMOVF(0-3)	Stream Overflow	Raw diagnostic stream control Overflow
			3	${DEVICE}:DAQMUX${DAQMUX#}_STRMERR(0-3)	Stream Error	Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
			4	${DEVICE}:DAQMUX${DAQMUX#}_INPDATAVALID(0-3)	Input Data valid	The incoming data is Valid (Usually connected to JESD valid signal).
			5	${DEVICE}:DAQMUX${DAQMUX#}_STRMENABLED(0-3)	Stream Enable	Output stream enabled.
			31:6	${DEVICE}:DAQMUX${DAQMUX#}_FRAMECNT(0-3)	Frame Count	Number of 4096 byte frames sent
	024-0x2F				Not used
DataFormat	0x30-0x33	RW	4:0	${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGNWIDTH(0-3)	Format Sign Width	Indicating sign extension point
			5	${DEVICE}:DAQMUX${DAQMUX#}_FORMATDATAWIDTH(0-3)	Format Data Width	Data width 32-bit or 16-bit '0' : 32-bits '1' : 16-bits
			6	${DEVICE}:DAQMUX${DAQMUX#}_FORMATSIGN(0-3)	Format Sign	Signed/unsigned '0' : Unsigned '1' : Signed
			7	${DEVICE}:DAQMUX${DAQMUX#}_DECIMATION(0-3)	Decimation Averaging	Decimation Averaging '0' : Disable '1' : Enable
				${DEVICE}:DAQMUX${DAQMUX#}_TRGDAQ		A sequence setting Software Trigger Enable to 1 then 0

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	Not in original requirements document
	Not exported to EPICS

*Data Header structure

HeaderWord[0]: dmod(31:0)
HeaderWord[1]: dmod(63:32)
HeaderWord[2]: dmod(95:64)
HeaderWord[3]: dmod(127:96)
HeaderWord[4]: dmod(159:128)
HeaderWord[5]: dmod(191:160)
HeaderWord[6]: timeStamp_i(31:0) – secPastEpoch
HeaderWord[7]: timeStamp_i(63:32) – nses
HeaderWord[8]: bsa(127:96) - edefAvgDn
HeaderWord[9]: bsa(95:64) -edefMinor
HeaderWord[10]: bsa(63:32) -edefMajor
HeaderWord[11]: bsa(31:0) -edefInit
HeaderWord[12]: packetSize_i
HeaderWord[13]:
- [BIT31:BIT27] = "00000"
- [BIT26:BIT26] = Trigger Header: Hardware Trigger – s_trigHw
- [BIT25:BIT25] = Trigger Header: Cascaded Trigger – s_trigCascRe
- [BIT24:BIT24] = Trigger Header: Software Trigger – s_trigSw
- [BIT23:BIT23] = Data format – dec16or32_i
- [BIT22:BIT22] = Enable decimation averaging – averaging_i
- [BIT21:BIT21] = Test mode – test_i
- [BIT20:BIT20] = AMC BAY Index – BAY_INDEX_G
- [BIT19:BIT16] = Channel Index – axiNum_i
- [BIT15:BIT00] = decimation rate divide – rateDiv_i

How to get the DaqMux streams

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How to get the DaqMux streams