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Register name

Address

AccessBitsPV Name ( postfix only # indicate mux# )Sub-nameDescription

Control

0x0RW

0


Software Trigger Enable

Triggers DAQ on all enabled channels

1DAQMUX#_CSCDTRGCascade Sw Trigger mask

Mask for enabling/disabling cascaded trigger

  • '0' - Disabled (Cascaded Sw Trigger ignored)
  • '1' - Enabled
2DAQMUX#_AUTOREARMAuto Rearm Hw Trigger

Mask for enabling/disabling hardware trigger. If disabled it has to be rearmed by ArmHwTrigger.

  • '0' - Disabled (has to be armed with bit3 otherwise disabled)
  • '1' - Enabled
3DAQMUX#_ARMHWTRGArm HW TriggerArms the hardware trigger on rising edge. After trigger occurs the trigger has to be rearmed.
4DAQMUX#_CLRTRGSTTrigger Clear StatusTrigger status will be cleared (On the rising edge).
5DAQMUX#_DAQMODEDAQ Mode

Select the data acquisition mode

  • '0' - Trigger mode - Normal DAQ mode.
    • Has to be triggered to start (Other reqs. to start: Enabled, dataValid, tReady, pause).
    • Stream stops if Error occurs.
  • '1' - Continuous mode- The data is framed and continuously streamed out after enabled.
    •  Has to be triggered to start (Other reqs. to start: Enabled, dataValid, tReady, pause).
    • Disable the stream to stop.
    • Freeze buffers inserts flag into the tUser bit at tLast
    • Stream stops if Error occurs.
6DAQMUX#_PACKETHEADERPacket Header Enable

Add 128-bit header (otherwise data will be inserted)(Applies only to Triggered mode)

  • '0' - Disabled
  • '1' - Enabled
7DAQMUX#_FRZBUFSw Freeze Buffer Freezes all enabled circular buffers
8DAQMUX#_HWFRZHw Freeze Buffer Mask

Mask for enabling/disabling hardware freeze buffer request

  • '0' - Disabled
  • '1' - Enabled
Status0x1RO

0


Software Trigger Status

Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] ).

1
Cascade Trigger StatusCascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
2
HW Trigger StatusHardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control[4] )
3
HW Trigger Armed StatusHardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control[3] - and cleared when hardware trigger occurs )
4
Combined Trigger StatusCombined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control[4] )
5
Freeze Buffers Status Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control[4] )
Decimation0x2RW15:0DAQMUX#_DECRATEDIVDecimation Rate Divider

Sample rate divider (Decimator):

  • Averaging Enabled: (powers of two) 1,2,4,8,16,etc (max 2^12)
  • Averaging Disabled (32-bit): 1,2,3,4,etc (max 2^16-1).
  • Averaging Disabled (16-bit): 1,2,4,6,8,etc (max 2^16-1).


DataSize0x3RW
DAQMUX#_BUFFSIZEData Buffer Size

Number of 32-bit words (if enabled header will be included in the first 14 words of data).

  • Minimum size is 14 (the size of the header).
TimeStamp0x4RO31:0DAQMUX0_TS_NSECTimestamp[31:0]Timestamp [31:0] - secPastEpoch
0x5RO31:0DAQMUX0_TS_SECTimestamp[63:32]Timestamp [63:32] - nsec
BSA0x6RO31:0
bsa(0)

edefAvgDn

0x731:0
bsa(1)edefMinor
0x831:0
bsa(2)edefMajor
0x931:0
bsa(3)edefInit
TrigCount0xARO31:0DAQMUX#_TRGCNTTrigger CountCounts valid data acquisition triggers.
DbgInputValid0xBRO31:0DAQMUX#_DBGINPVALIDDebug Input Valid BusInput Valid bus for debugging
DbgLinkReady0xCRO31:0DAQMUX#_DBGLNKRDYDebug Link ReadyInput LinkReady bus for debugging
InputMuxSel0x10RW4:0

DAQMUX#_INPMUXSELSTR0

DAQMUX#_INPMUXSEL0

Input Mux Select[0]

0x1x: Stream x: Channel select Multiplexer 

0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29)

Test mode will output counter data

0x114:0

DAQMUX#_INPMUXSELSTR1

DAQMUX#_INPMUXSEL1

Input Mux Select[1]
0x124:0

DAQMUX#_INPMUXSELSTR2

DAQMUX#_INPMUXSEL2

Input Mux Select[2]
0x134:0

DAQMUX#_INPMUXSELSTR3

DAQMUX#_INPMUXSEL3

Input Mux Select[3]
0x14-0x1F
-Not used
DaqStatus0x20-0x23RO0

DAQMUX#_STRMPAUSE(0-3)

Stream Pause

Raw diagnostic stream control Pause

1DAQMUX#_STRMRDY(0-3)Stream ReadyRaw diagnostic stream control Ready
2DAQMUX#_STRMOVF(0-3)Stream OverflowRaw diagnostic stream control Overflow
3DAQMUX#_STRMERR(0-3)Stream ErrorError during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped)
4DAQMUX#_INPDATAVALID(0-3)Input Data validThe incoming data is Valid (Usually connected to JESD valid signal).
5DAQMUX#_STRMENABLED(0-3)Stream EnableOutput stream enabled.
31:6DAQMUX#_FRAMECNT(0-3)Frame CountNumber of 4096 byte frames sent
024-0x2F

Not used
DataFormat0x30-0x33RW4:0DAQMUX#_FORMATSIGNWIDTH(0-3)Format Sign WidthIndicating sign extension point



5DAQMUX0_FORMATDATAWIDTH(0-3)Format Data Width

Data width 32-bit or 16-bit

  • '0' : 32-bits
  • '1' : 16-bits



6DAQMUX#_FORMATSIGN(0-3)Format Sign

Signed/unsigned

  • '0' : Unsigned
  • '1' : Signed



7DAQMUX#_DECIMATION(0-3)Decimation Averaging

Decimation Averaging

  • '0' : Disable
  • '1' : Enable



Sequence PVs

EM1K0:GMD:HPS:DAQMUX0_TRGDAQ. Sets TriggerSw to 1 then 0.