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Register name | Address | Access | Bits | PV Name | Sub-name | Description | |||||
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Control | 0x0 | RW | 0 | Software Trigger Enable | Triggers DAQ on all enabled channels | ||||||
1 | Cascade Sw Trigger mask | Mask for enabling/disabling cascaded trigger
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2 | Auto Rearm Hw Trigger | Mask for enabling/disabling hardware trigger. If disabled it has to be rearmed by ArmHwTrigger.
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3 | bit3: Arm Hardware HW Trigger ( | Arms the hardware trigger on rising edge). After trigger occurs the trigger has to be rearmed. | |||||||||
4 | bit4: Trigger Clear Status | Trigger status will be cleared (On the rising edge). | |||||||||
5 | bit5: DAQ Mode | Select the data acquisition mode
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6 | Packet Header Enable | bit6: Add 128-bit header (otherwise data will be inserted)(Applies only to Triggered mode)
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7 | Sw Freeze Buffer | Freezes bit7: Software freeze buffer (Freezes all enabled circular buffers) | |||||||||
8bit8 | Hw Freeze Buffer Mask | Mask for enabling/disabling hardware freeze buffer request
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Status | 0x1 | RO | 0 | Software Trigger Status | bit0: Software Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control([4))bit1: ] ). | ||||||
1 | Cascade Trigger Status | Cascade Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control([4)] ) | |||||||||
2 | HW Trigger Status | )bit2: Hardware Trigger Status (Registered on first trigger until cleared by Trigger Clear Status - Control([4))] ) | |||||||||
3 | HW Trigger Armed Status | bit3: Hardware Trigger Armed Status (Registered on rising edge Arm HW Trigger - Control([3) ] - and cleared when Hw hardware trigger occurs ) | |||||||||
4 | Combined Trigger Status | bit4: Combined Trigger Status (Registered when trigger condition is met until cleared by Trigger Clear Status - Control([4))] ) | |||||||||
5 | Freeze Buffers Status | bit5: Freeze buffer occurred (Registered on first freeze until cleared by Trigger Clear Status - Control([4)] ) | |||||||||
Decimation | 0x2 | RW | bit 15-:0 | Decimation Rate Divider | Sample rate divider (Decimator):Only
Comment: If only powers of two allowed: why not encode this way? 0..16 (bit 4..0) A: We will also have an option to disable averaging (Steve needs data without averaging). If the Averaging will be disabled also other decimation factors will be allowed DataFormat(7) Comment: Do we need to set decimation per channel? The samples will be averaged (running average filter with powers of 2 window size
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DataSize | 0x3 | RW | Data buffer size.Buffer Size | - Number of 32-bit words (if enabled header will be included in the first 14 words of data). -
Comment: Not sure this is more confusing than beneficial. IMO we should just use one of these. A: Agree we will use number of 32-bit words as in old version. | |||||||
TimeStamp | 0x4 | RO | 31:0 | TimestampTimeStamp[31:0] | 0x4 | RO | Timestamp [31:0] - secPastEpoch | ||||
0x5 | RO | 31:0 | TimestampTimeStamp[63:32] | 0x5 | RO | Timestamp [63:32] - nsec | |||||
BSA | 0x6 | RO | 31:0 | bsa(0) | edefAvgDn | ||||||
0x7 | 31:0 | bsa(1) | edefMinor | ||||||||
0x8 | 31:0 | bsa(2) | edefMajor | ||||||||
0x9 | 31:0 | bsa(3) | edefInit | ||||||||
TrigCount | 0xA | RO | 31:0 | Trigger Count | Counts valid data acquisition triggers. | ||||||
DbgInputValid | 0xB | RO | 31:0 | Debug Input Valid Bus | Input Valid bus for debugging | ||||||
DbgLinkReady | 0xC | RO | 31:0 | Debug Link Ready | Input LinkReady bus for debugging | ||||||
InputMuxSel | 0x10 | RW | 4:0 | Input Mux Select[0] | Multiplexer | 0x10-0x1F | RW | 0x1x: Stream x: Channel select Multiplexer 0 - Disabled, 1 - Test, 2 - Ch0, 3 - Ch1, 4 - Ch2 etc.(up to Ch29) | Test mode will output counter data | ||
0x11 | 4:0 | Input Mux Select[1] | |||||||||
0x12 | 4:0 | Input Mux Select[2] | |||||||||
0x13 | 4:0 | Input Mux Select[3] | |||||||||
0x14-0x1F | Not used | ||||||||||
DaqStatus | 0x20- | 0x2F0x23 | RO | 0 | 0x2x: Stream x DaqStatus:bit 0: Pause | Raw diagnostic stream control Pause | |||||
bit 1 | Stream Ready | : Raw diagnostic stream control Readybit | |||||||||
2 | Stream Overflow | : Raw diagnostic stream control Overflowbit | |||||||||
3 | Stream Error | : Error during last Acquisition (Raw diagnostic stream control Ready or incoming data valid dropped) bit 4: Incoming data lane valid bit 5: DAQ Enabled bit 31-6: Number of packets (4k byte frames) sent | |||||||||
4 | Input Data valid | The incoming data is Valid (Usually connected to JESD valid signal). | |||||||||
5 | Stream Enable | Output stream enabled. | |||||||||
31:6 | Frame Count | Number of 4096 byte frames sent | |||||||||
024-0x2F | Not used | ||||||||||
DataFormat | 0x30-0x33 | RW | 4:0 | Format Sign Width | Indicating sign extension point | ||||||
5 | Format Data Width | Data width 32-bit or 16-bit
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6 | Format Sign | Signed/unsigned
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7 | Decimation Averaging | Decimation Averaging
| DataFormat | 0x30-0x3F | RW | TBD | TBD |