Requirements
- SUGOI = SLAC Ultimate Gateway Operational Interface
- Targeted for ASIC register communication and timing/trigger synchronization
- Support "point-to-point " only
communication - Serial Encoding:
coding ( 8B10B ) or scrambler (16B18B, 32B34B or 64B66B)???Must be DC balanced - Assuming "clock synchronous" system
- Clock will be fan out to both endpoints
- No CDR required
- IDELAY/ODELAY to deskew data lane
- No "clock correction pattern" required
- Support interleaved data streaming and sideband controls
- deterministic trigger and control delivery for sideband
- Virtual channel support????
- Up to ??? virtual channels
- Interleaved virtual channel support???
- Bit error correction is not supported
- Bit error detection:
- CRC or checksum???
- Only both data stream and sidebad or data stream only???
- Ability to inject bit error for testing protocol
- )
- Targeting communication to ASIC over fiber optic or long copper cables
- Serial Rate: Same as reference clock sent to ASIC
- Supports fixed latency communication What should happen when a bit error is detected?
{"serverDuration": 48, "requestCorrelationId": "430b31cefd05fedd"}