...
- Support "point-to-point" only
- 8B10B line coding
- DC balanced
- Selected line coding (8B10B) over scrambler (64B66B) to minimize logic on the ASIC side
- Assuming "clock synchronous" system
- Clock will be fan out to both endpoints
- No CDR required
- IDELAY/ODELAY to deskew data lane
- No "clock correction pattern" required
- Support interleaved data streaming and sideband controls
- deterministic trigger and control delivery for sideband
- Virtual channel support????
- Up to ??? virtual channels
- Interleaved virtual channel support???
- Bit error detection:
- CRC or checksum???
- Only both data stream and sidebad or data stream only???
- Bit error correction is not suported
{"serverDuration": 49, "requestCorrelationId": "f785c592d4aa3360"}