Page History

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• Support "point-to-point" only
  
  • No network support
• 8B10B line coding
  • DC balanced
  • Less resource for Selected line coding (8B10B) over scrambler (64B66B) to minimize logic on the ASIC side
• Assuming "clock synchronous" system
  • Clock will be fan out to both endpoints
  • No CDR required
  • IDELAY/ODELAY to deskew data lane
  • No "clock correction pattern" required
• Support data streaming and sideband controls
  
  • deterministic trigger and control delivery for sideband
• Virtual channel support????
  • Up to ??? virtual channels
     
  • Interleaved virtual channel support???