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prescaling data by x amount over registersimulation of modules inside TimeToolCore.vhd- scaled background subtraction
- peak-finding (final parameters)
- programming weights by axi-stream
- emulate LCLS2 timing system in firmware
- add the goose
virtual evg. (should only require gui tweaks. check with ILA)- how to handle the git large files
get rid of guigui fully removed,- still need to make smart and stream line
programmable event-code & trigger delay (axi bus)emulate epix model (send timestamp to front-end board. time stamp should be at the beginning of image packet.). later: maybe this isn't necessary because in future we would support camlink-over-fiber cameras with no front-end board?save hdf5full/deca mode (only 8 bit for deca or full)get test stand in 901 working- start with Matt matched filter algorithm or Abdullah algorithm
- feedback results to Joe Frisch as udp packets or accelerator-style-pgp
is 8-bits OK for deca? (answer: yes, for interferometry mode)- understand how system behaves at high rates (do we drop frames? timestamps correct?)
- reuse matt's firmware for timestamping
- add in LCLS2 timing (triggering)
- send full signal to Matt
- switch from python to C
- think about running the camera all the time (to send feedback data continuously)
- difference kc705 revisions 1.1 vs 1.2.: no significant difference according to https://www.xilinx.com/support/answers/59751.html. Either an FMC problem, or subtle timing issue, or need to specify board rev somehow when synthesizing?
- interface to DRP?
new front-end boardstouch base with Ryan on code structure issues- prepare for running in LCLS-I? If yes:
- spy on the timestamp multicasts in software (maybe not necessary)
take real pictures with lens from Ryantrigger delay and event-code programmable via AXIeliminate gui and save hdf5put all setup commands in python scriptdo we need feedback for laser? (no)- run at 120Hz overnight and validate
resolve vhdl axi-lite offset constantswhy doesn't offset 0x400000 (which turns into 0xc00000) work?https://forums.xilinx.com/t5/Synthesis/How-to-display-post-synthesis-integer-constant-values/td-p/692285
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