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• also needed:
• under "commands" tab need to ConfigLclsTimingV1.  this controls a multiplexer that routes the evr clock/data to the fpga, either from lcls1 or lcls2

 see ILA core generation visual step through for walk through on how to setup.

Simulation tools

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug937-vivado-design-suite-simulation-tutorial.pdf

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